Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Ultra-low power digital subthreshold logic circuits
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Robust subthreshold logic for ultra-low power operation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Sub-Domino Logic: Ultra-Low Power Dynamic Sub-Threshold Digital Logic
VLSID '01 Proceedings of the The 14th International Conference on VLSI Design (VLSID '01)
Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing
Proceedings of the 43rd annual Design Automation Conference
Six subthreshold full adder cells characterized in 90 nm CMOS technology
DDECS '06 Proceedings of the 2006 IEEE Design and Diagnostics of Electronic Circuits and systems
Design-Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable Datapath
VLSID '09 Proceedings of the 2009 22nd International Conference on VLSI Design
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Arithmetic circuits have always played one of the most important roles in the designs of processors, FPGAs, and the rapidly evolving domain of media processing architectures. The full adder cell forms the basic building block of majority of these arithmetic circuits. In this paper we describe a hybrid pseudo static full adder cell designed using Data Driven Dynamic Logic. Simulation results show the adder to out perform its competitors, both static as well as dynamic topologies in terms of performance, while maintaining relatively similar area and power characteristics. This paper presents a complete characterization of the popular adder cells in terms of delay, area, power, noise margin and reliability analysis for both super threshold and sub threshold operating regimes.