Sub-Domino Logic: Ultra-Low Power Dynamic Sub-Threshold Digital Logic

Authors:
Hendrawan Soeleman;Kaushik Roy;Bipul Paul
Affiliations:
-;-;-
Venue:
VLSID '01 Proceedings of the The 14th International Conference on VLSI Design (VLSID '01)
Year:
2001

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Abstract

Sub-threshold static and ratioed logic have recently been proposed to satisfy the ultra-low power requirement in applications such as hearing aid, pace-maker, wearable wrist-watch computer etc. These logic circuits, however, can be operated only at lower frequencies due to lower supply voltage. To increase the frequency of operation, we propose sub-threshold dynamic logic: Sub-Domino logic. A standard full-adder circuit is implemented in both Sub-Domino and Sub-CMOS logic operating in the subthreshold region. Simulation results show that Sub-Domino logic has lower power consumption, smaller area (60% of Sub-CMOS logic), and is 3 times faster than Sub-CMOS logic. It is also shown that Sub-Domino logic has excellent noise margin.