Body-bias compensation technique for SubThreshold CMOS static logic gates

Authors:
Luiz Alberto P. Melek;Márcio C. Schneider;Carlos Galup-Montoro
Affiliations:
Universidade Federal de Santa Catarina, Florianópolis-SC-Brazil;Universidade Federal de Santa Catarina, Florianópolis-SC-Brazil;Universidade Federal de Santa Catarina, Florianópolis-SC-Brazil
Venue:
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Year:
2004

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Abstract

This paper analyzes the performance of the conventional CMOS inverter, NAND-2 and NOR-2 static logic gates operating in the subthreshold region. The dependence of the drain currents on the process parameters can give rise to drive currents of NMOS and PMOS transistors that differ by an order of magnitude or even more. To compensate for this difference in currents, we propose three bias circuits in single-well processes that adjust the body voltage. Computer simulations using the AMS 0.8um technology and the BSIM3v3 model were carried out to assess the compensation technique. A test chip was fabricated in both AMIS 1.5um and TSMC0.35um to further validate the proposal.