Performance enhancement of subthreshold circuits using substrate biasing and charge-boosting buffers

Authors:
Sumanth Amarchinta;Dhireesha Kudithipudi
Affiliations:
Rochester Institute of Technology, Rochester, NY, USA;Rochester Institute of Technology, Rochester, NY, USA
Venue:
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Year:
2010

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Abstract

Subthreshold circuits are ideal for ultra low power applications. However, they suffer from low operating speeds. By improving the speed of subthreshold circuits their application spectrum can be expanded. In this paper, two existing biasing methods and a new approach to substrate biasing to improve the performance of subthreshold circuits is presented. We derive an approximate expression for the drain current of MOS transistor when substrate biased. We also present a new performance enhancement technique using charge-boosting-buffers to improve the performance of subthreshold circuits. A performance-enhanced standard cell library is built by implementing these techniques on a standard subthreshold cell library. When the enhanced library is applied on ISCAS85 benchmark circuits a 10 times improvement in frequency with an overhead of approximately 2 times in the energy-delay product is observed.