Robust ultra-low power sub-threshold DTMOS logic

Authors:
Hendrawan Soeleman;Kaushik Roy;Bipul Paul
Affiliations:
Purdue University, Department of Electrical and Computer Engineering, West Lafayette, IN;Purdue University, Department of Electrical and Computer Engineering, West Lafayette, IN;Purdue University, Department of Electrical and Computer Engineering, West Lafayette, IN
Venue:
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Year:
2000

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Abstract

Digital sub-threshold logic circuits have recently been proposed for applications in the ultra-low power end of the design spectrum, where the performance is of secondary importance. To improve switching performance of the sub-threshold logic family with comparable energy/switching, we propose the use of sub-DTMOS (sub-threshold Dynamic Threshold MOS) transistors. The stability of sub-threshold DTMOS logic to temperature and process variations eliminates the need of additional stabilization scheme that may be required for regular sub-threshold MOS logic families to ensure proper operation in the sub-threshold region.