Digital CMOS logic operation in the sub-threshold region
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Robust ultra-low power sub-threshold DTMOS logic
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Robust subthreshold logic for ultra-low power operation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Predictive technology model for nano-CMOS design exploration
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Subthreshold Pass Transistor Logic for Ultra-Low Power Operation
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Utilizing reverse short-channel effect for optimal subthreshold circuit design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Robustness comparison of emerging devices for portable applications
Journal of Nanomaterials
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Double gate FinFETs are shown to be better candidates for subthreshold logic design than equivalent bulk devices. However it is not so clear which configuration of DG FinFETs will be more optimal for subthreshold logic. In this paper, we compare the different device and circuit level performance metrics of DG FinFETs with symmetric, asymmetric, tied and independent gate options for subthreshold logic. We observe that energy delay product (EDP) shows a better subthreshold performance metric than power delay product (PDP) and it is observed that the tied gate symmetric option has ~78% lower EDP value than that of independent gate option for subthreshold logic. The asymmetry in back gate oxide thickness adds to further reduction in EDP for tied gate and has no significant effect on independent gate option. The robustness (measured in terms of % variation in device/circuit performance metrics for a +/-10% variation in design parameters) of DG FinFETs with various options has also been investigated in presence of different design parameter variations such as silicon body thickness, channel length, threshold voltage, supply voltage and temperature, etc. Independent gate option has been seen to be more robust (~40% less) than that of tied gate option for subthreshold logic. Comparison of logic families for subthreshold regime with DG FinFET options shows that for tied gate option, sub-CMOS, sub-Domino and sub-DCVSL have almost similar and better energy consumption and robustness characteristics with respect to PVT variations than other families.