Digital CMOS logic operation in the sub-threshold region

Authors:
Hendrawan Soeleman;Kaushik Roy
Affiliations:
Purdue University, Department of Electrical and Computer Engineering, West Lafayette, IN;Purdue University, Department of Electrical and Computer Engineering, West Lafayette, IN
Venue:
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Year:
2000

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Abstract

Numerous efforts in balancing the trade-off between power, area and performance have been carried out in the medium performance, medium power region of the design spectrum. However, not much study has been done at the two extreme ends of the design spectrum, namely, the ultra-low power with acceptable performance at one end, and high performance with power within limit at the other. In this paper, we focus on the ultra-low power end of the spectrum where performance is of secondary importance. One solution to achieve the ultra-low power requirement is to operate the digital logic gates in sub-threshold region. In this paper, we analyze both CMOS and Pseudo-NMOS logic operating in sub-threshold region. We compare the results with CMOS in normal strong inversion region and with other known low-power logic, namely, energy recovery logic. Results show energy/switching reduction of two orders of magnitude from an 8×8 carry-save array multiplier when it is operated in the sub-threshold region.