Ultra-low power digital subthreshold logic circuits
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Filtering Memory References to Increase Energy Efficiency
IEEE Transactions on Computers
Digital CMOS logic operation in the sub-threshold region
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
VLSI interconnect repeater for sub-threshold applications: a novel approach
ICNVS'10 Proceedings of the 12th international conference on Networking, VLSI and signal processing
Efficient interconnect design with novel repeater insertion for low power applications
WSEAS Transactions on Circuits and Systems
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The need of popular portable electronics for long battery life is placing power reduction at the top of every IC design engineer's to-do list. A new breed of design automation tools is helping them scrimp on power at every step of the VLSI design process. The automation tools can be differentiated, to a first order, by the level of abstraction on which they operate. Lowest of all are the transistor level tools. These possess the best accuracy, but commensurately require the longest run times and have the smallest capacities-the size of the circuit that can be analyzed. While transistor level tools can assist with analyses earlier in the design process, they are typically used to characterize cells and modules for use at the higher abstraction levels. The next level of abstraction embraces the logic-level power analysis tools. The highest abstraction level for which power analysis tools exist today is the architectural level. This type of tool analyzes abstract design representations such as Verilog or VHDL RTL code. The use of these tools in power reduction design is outlined