Digital CMOS logic operation in the sub-threshold region
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Robust subthreshold logic for ultra-low power operation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Analyzing and modeling process balance for sub-threshold circuit design
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Analysis of energy reduction on dynamic voltage scaling-enabled systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Digital circuit designs in subthreshold region have been studied in recent years. Their works focus on special purpose for some digital applications in low frequency. This paper proposed modeling analysis of each CMOS logic cell operating at subthreshold region. We explore the delays and power dissipation of logic cell and make scaled factors mapping from typical voltage to sub-threshold voltage conditions. We evaluated the minimum requirement for 4 bits, 6 bits and 10 bits orthogonal frequency division multiplexing (OFDM) demodulator to operate in sub-threshold region. The simulation results are characteristics of OFDM wireless communication system when it operates at low voltage. It also clearly shows that low voltage is not a barrier for large-scale digital circuits to operate under the threshold voltage.