A novel VLSI layout fabric for deep sub-micron applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Ultra-low power digital subthreshold logic circuits
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Digital CMOS logic operation in the sub-threshold region
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Robust subthreshold logic for ultra-low power operation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Cross-talk immune VLSI design using a network of PLAs embedded in a regular layout fabric
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A metal and via maskset programmable VLSI design methodology using PLAs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Minimum Energy Near-threshold Network of PLA based Design
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Implementation of MOSFET based capacitors for digital applications
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
A design flow to optimize circuit delay by using standard cells and PLAs
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
A PLA based asynchronous micropipelining approach for subthreshold circuit design
Proceedings of the 43rd annual Design Automation Conference
Variation-driven device sizing for minimum energy sub-threshold circuits
Proceedings of the 2006 international symposium on Low power electronics and design
A low-power parallel design of discrete wavelet transform using subthreshold voltage technology
CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture
HiPEAC '09 Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers
Slew-aware clock tree design for reliable subthreshold circuits
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Variation resilient adaptive controller for subthreshold circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Hybrid super/subthreshold design of a low power scalable-throughput FFT architecture
Transactions on High-Performance Embedded Architectures and Compilers IV
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Due to their extreme low power consumption, sub-threshold design approaches are appealing for a widening class of applications which demand low power consumption and can tolerate larger circuit delays. However, sub-threshold circuits are extremely sensitive to variations in supply, temperature and processing factors. In this paper, we present a sub-threshold design methodology which dynamically self-adjusts for inter and intra-die process, supply voltage and temperature (PVT) variations. This adjustment is achieved by performing bulk voltage adjustments in a closed-loop fashion, using a charge pump and a phase-detector.