Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
A novel VLSI layout fabric for deep sub-micron applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Ultra-low power digital subthreshold logic circuits
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Digital CMOS logic operation in the sub-threshold region
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Robust subthreshold logic for ultra-low power operation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
River PLAs: a regular circuit structure
Proceedings of the 39th annual Design Automation Conference
Whirlpool PLAs: a regular logic structure and their synthesis
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Theoretical and practical limits of dynamic voltage scaling
Proceedings of the 41st annual Design Automation Conference
A variation tolerant subthreshold design approach
Proceedings of the 42nd annual Design Automation Conference
A metal and via maskset programmable VLSI design methodology using PLAs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Design at the end of the silicon roadmap
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
PLA-based regular structures and their synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A PLA based asynchronous micropipelining approach for subthreshold circuit design
Proceedings of the 43rd annual Design Automation Conference
Pipelined network of PLA based circuit design
Proceedings of the 18th ACM Great Lakes symposium on VLSI
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In recent times, there has been a significant growth in applications for battery powered portable electronics, as well as low power sensor networks. While sub-threshold circuit design approaches can reduce the power consumption significantly, a design operating at sub-threshold voltages is not necessarily optimal in terms of energy consumption. In this paper, we describe a technique to find the energy optimum VDD value for a design, and show that for minimum energy consumption, the circuit should be operated at VDD values which are above the NMOS threshold voltage value. We study this problem in the context of designing a circuit using a network of dynamic NOR-NOR PLAs.