Programming perl
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Exploring regular fabrics to optimize the performance-cost trade-off
Proceedings of the 40th annual Design Automation Conference
Design Methodology for a 1.0 GHz Microprocessor
ICCD '98 Proceedings of the International Conference on Computer Design
Exploring Logic Block Granularity for Regular Fabrics
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Heterogeneous Programmable Logic Block Architectures
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
HARP: hard-wired routing pattern FPGAs
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
A variation tolerant subthreshold design approach
Proceedings of the 42nd annual Design Automation Conference
Minimum Energy Near-threshold Network of PLA based Design
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
A design flow to optimize circuit delay by using standard cells and PLAs
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
High-throughput VLSI Implementations of Iterative Decoders and Related Code Construction Problems
Journal of VLSI Signal Processing Systems
Pipelined network of PLA based circuit design
Proceedings of the 18th ACM Great Lakes symposium on VLSI
A lithography-friendly structured ASIC design approach
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Transistor-level layout of high-density regular circuits
Proceedings of the 2009 international symposium on Physical design
Buffer design and optimization for lut-based structured ASIC design styles
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Performance study of VeSFET-based, high-density regular circuits
Proceedings of the 19th international symposium on Physical design
Layout generator for transistor-level high-density regular circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Via configurable three-input lookup-tables for structured ASICs
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Designing via-configurable logic blocks for regular fabric
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Area impact analysis of via-configurable regular fabric for digital integrated circuit design
Proceedings of the 24th symposium on Integrated circuits and systems design
Standard cell like via-configurable logic blocks for structured ASIC in an industrial design flow
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Architecture and design flow for a highly efficient structured ASIC
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Routability optimization for crossbar-switch structured ASIC design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A regular fabric design methodology for applications requiring specific layout-level design rules
Microelectronics Journal
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In recent times there has been a substantial increase in the cost and complexity of fabricating a VLSI chip. The lithography masks themselves can cost between /spl epsi/ and /spl ges/. It is conjectured that due to these increasing costs, the number of ASIC starts in the last few years has declined. We address this problem by using an array of dynamic PLAs which require only metal and via mask customization in order to implement a new design. This would allow several similar-sized designs to share the same base set of masks (right up to the metal layers) and only have different metal and via masks. We have implemented our methodology for both combinational and sequential designs, and demonstrate that our approach strikes a reasonable compromise between ASIC and field programmable design methodologies in terms of placed-and-routed area and delay. Our method has a 2.89/spl times/ (3.58/spl times/) delay overhead and a 4.96/spl times/ (3.44/spl times/) area overhead compared to standard cells for combinational (sequential) designs.