An architectural exploration of via patterned gate arrays
Proceedings of the 2003 international symposium on Physical design
Exploring regular fabrics to optimize the performance-cost trade-off
Proceedings of the 40th annual Design Automation Conference
Exploring Logic Block Granularity for Regular Fabrics
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Design methodology and tools for NEC electronics' structured ASIC ISSP
Proceedings of the 2004 international symposium on Physical design
Design considerations for regular fabrics
Proceedings of the 2004 international symposium on Physical design
Structured ASIC, evolution or revolution?
Proceedings of the 2004 international symposium on Physical design
Design automation for mask programmable fabrics
Proceedings of the 41st annual Design Automation Conference
A metal and via maskset programmable VLSI design methodology using PLAs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A lithography-friendly structured ASIC design approach
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Standard Cell Like Via-Configurable Logic Block for Structured ASICs
ISVLSI '08 Proceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI
A comparison of via-programmable gate array logic cell circuits
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Why design must change: rethinking digital design
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Via configurable three-input lookup-tables for structured ASICs
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Designing via-configurable logic blocks for regular fabric
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Measuring the Gap Between FPGAs and ASICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Performance and Cost Tradeoffs in Metal-Programmable Structured ASICs (MPSAs)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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As fabrication process technology continues to advance, mask set costs have become prohibitively expensive. Structured application specific integrated circuits (sASICs) offer a middle ground in price and performance between ASICs and field-programmable gate arrays (FPGAs) by sharing masks across different designs. In this paper, two sASIC architectures are proposed, the first being based on three-input lookup-tables, and the second on AOI22 gates. The sASICs are programmed using a standard-cell compatible design flow. They are customized using a minimum of three masks, i.e., two metals and one via. The area and delay of the sASIC are compared with ASICs and FPGAs. Results over a set of benchmark circuits show that our AOI22-based sASIC had an average of 1.76×/1.41× increase in area/delay compared to ASICs, a considerable improvement compared with the 26.56×/5.09× increase for FPGAs. This is, to the best of our knowledge, the best performance reported in the literature for a practical sASIC. A prototype using the sASIC was fabricated using a universal machine control 0.13-µm mixed-mode/RF process. It was fully verified using scan and functional tests, and used in a demonstration system.