Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
FPGA routing architecture: segmentation and buffering to optimize speed and density
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
IC design in high-cost nanometer-technologies era
Proceedings of the 38th annual Design Automation Conference
FPGA switch block layout and evaluation
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Heterogeneous Programmable Logic Block Architectures
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Exploring regular fabrics to optimize the performance-cost trade-off
Proceedings of the 40th annual Design Automation Conference
Design methodology and tools for NEC electronics' structured ASIC ISSP
Proceedings of the 2004 international symposium on Physical design
Design considerations for regular fabrics
Proceedings of the 2004 international symposium on Physical design
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Design automation for mask programmable fabrics
Proceedings of the 41st annual Design Automation Conference
On designing via-configurable cell blocks for regular fabrics
Proceedings of the 41st annual Design Automation Conference
An integrated design flow for a via-configurable gate array
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Buffering global interconnects in structured ASIC design
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Via-configurable routing architectures and fast design mappability estimation for regular fabrics
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A methodology for FPGA to structured-ASIC synthesis and verification
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
Via-configurable routing architectures and fast design mappability estimation for regular fabrics
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Buffering global interconnects in structured ASIC design
Integration, the VLSI Journal
FPGA Architecture: Survey and Challenges
Foundations and Trends in Electronic Design Automation
A comparison of via-programmable gate array logic cell circuits
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Buffer design and optimization for lut-based structured ASIC design styles
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Via configurable three-input lookup-tables for structured ASICs
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Power gating design for standard-cell-like structured ASICs
Proceedings of the Conference on Design, Automation and Test in Europe
Performance-driven dual-rail insertion for chip-level pre-fabricated design
Proceedings of the Conference on Design, Automation and Test in Europe
Performance-driven dual-rail routing architecture for structured ASIC design style
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Designing via-configurable logic blocks for regular fabric
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Standard cell like via-configurable logic blocks for structured ASIC in an industrial design flow
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Architecture and design flow for a highly efficient structured ASIC
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Routability optimization for crossbar-switch structured ASIC design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A regular fabric design methodology for applications requiring specific layout-level design rules
Microelectronics Journal
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In this work we investigate the architecture of a Via Patterned Gate Array (VPGA) [1], focusing primarily on: 1) the optimal lookup table (LUT) size; and 2) a comparison the crossbar and switch block routing architectures. Unlike FPGAs, the routing architectures in a VPGA do not dominate the total area of the circuit. Therefore our results suggest that using smaller LUTs results in a much faster and smaller design. In the routing architecture comparison, our results also show that the switch block architecture is inferior to the crossbar architecture in terms of area utilization. As the number of routing tracks grows, the switch block architecture begins to dominate the total area of the design as in the case of the FPGAs.