Cost of silicon viewed from VLSI design perspective
DAC '94 Proceedings of the 31st annual Design Automation Conference
Design-manufacturing interface: Part I — vision
Proceedings of the conference on Design, automation and test in Europe
An algorithm for determining repetitive patterns in very large IC layouts
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Modeling the Economics of Testing: A DFT Perspective
IEEE Design & Test
An architectural exploration of via patterned gate arrays
Proceedings of the 2003 international symposium on Physical design
Synthesis and placement flow for gain-based programmable regular fabrics
Proceedings of the 2003 international symposium on Physical design
On-Chip Stochastic Communication
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
PIM lite: a multithreaded processor-in-memory prototype
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Towards on-chip fault-tolerant communication
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Computation and communication refinement for multiprocessor SoC design: A system-level perspective
Proceedings of the 41st annual Design Automation Conference
Structured and tuned array generation (STAG) for high-performance random logic
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Chip size estimation for SOC design space exploration
Journal of Systems Architecture: the EUROMICRO Journal
OPC-free and minimally irregular IC design style
Proceedings of the 44th annual Design Automation Conference
2.5-Dimensional VLSI system integration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A regular fabric design methodology for applications requiring specific layout-level design rules
Microelectronics Journal
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Nanometer IC technologies are on the horizon. They promise a lot. But will cost a lot as well. Therefore, we need to ask today: How may the billions of dollars, that we will have to spent on nanometer-fablines, affect IC design domain? This paper attempts to address the above question by analyzing the design-manufacturing interface. A partial answer is derived from a simple transistor cost model proposed in the body of the paper.