Statecharts: A visual formalism for complex systems
Science of Computer Programming
SIAM Journal on Applied Mathematics
Epidemic algorithms for replicated database maintenance
PODC '87 Proceedings of the sixth annual ACM Symposium on Principles of distributed computing
ACM Transactions on Computer Systems (TOCS)
Next century challenges: scalable coordination in sensor networks
MobiCom '99 Proceedings of the 5th annual ACM/IEEE international conference on Mobile computing and networking
Design methodologies for system level IP
Proceedings of the conference on Design, automation and test in Europe
IC design in high-cost nanometer-technologies era
Proceedings of the 38th annual Design Automation Conference
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
FOCS '00 Proceedings of the 41st Annual Symposium on Foundations of Computer Science
Communication Networks
A Modular Approach to Fault-Tolerant Broadcasts and Related Problems
A Modular Approach to Fault-Tolerant Broadcasts and Related Problems
The future of interconnection technology
IBM Journal of Research and Development
OCCN: a NoC modeling framework for design exploration
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
Enabling on-chip diversity through architectural communication design
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A continuous time markov decision process based on-chip buffer allocation methodology
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Design and analysis of an NoC architecture from performance, reliability and energy perspective
Proceedings of the 2005 ACM symposium on Architecture for networking and communications systems
Core Network Interface Architecture and Latency Constrained On-Chip Communication
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Evaluation of SEU and crosstalk effects in network-on-chip switches
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Applying stochastic modeling to bus arbitration for systems-on-chip
Integration, the VLSI Journal
SAPP: scalable and adaptable peak power management in nocs
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Proceedings of the 18th ACM Great Lakes symposium on VLSI
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
On reliable modular testing with vulnerable test access mechanisms
Proceedings of the 45th annual Design Automation Conference
Scalable and reliable communication for hardware transactional memory
Proceedings of the 17th international conference on Parallel architectures and compilation techniques
Fault tolerant mechanism to improve yield in NoCs using a reconfigurable router
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
NoC topology synthesis for supporting shutdown of voltage islands in SoCs
Proceedings of the 46th Annual Design Automation Conference
A routing algorithm for random error tolerance in network-on-chip
HCI'07 Proceedings of the 12th international conference on Human-computer interaction: applications and services
A low-overhead and reliable switch architecture for Network-on-Chips
Integration, the VLSI Journal
A flexible parallel simulator for networks-on-chip with error control
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fault-Tolerant Flow Control in On-chip Networks
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Transient and Permanent Error Co-management Method for Reliable Networks-on-Chip
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Complement routing: A methodology to design reliable routing algorithm for Network on Chips
Microprocessors & Microsystems
Electromigration-aware dynamic routing algorithm for network-on-chip applications
International Journal of High Performance Systems Architecture
Reliability analysis of on-chip communication architectures: An MPEG-2 video decoder case study
Microprocessors & Microsystems
On the design and analysis of fault tolerant NoC architecture using spare routers
Proceedings of the 16th Asia and South Pacific Design Automation Conference
A reliable and power efficient flow-control method to eliminate crosstalk faults in network-on-chips
Microprocessors & Microsystems
An operating system infrastructure for fault-tolerant reconfigurable networks
ARCS'06 Proceedings of the 19th international conference on Architecture of Computing Systems
A fault tolerant approach to object oriented design and synthesis of embedded systems
LADC'05 Proceedings of the Second Latin-American conference on Dependable Computing
Networks on chips: structure and design methodologies
Journal of Electrical and Computer Engineering - Special issue on Networks-on-Chip: Architectures, Design Methodologies, and Case Studies
An efficient routing methodology to tolerate static and dynamic faults in 2-D mesh networks-on-chip
Microprocessors & Microsystems
Improving a fault-tolerant routing algorithm using detailed traffic analysis
HPCC'07 Proceedings of the Third international conference on High Performance Computing and Communications
Reliable and adaptive network-on-chip architectures for cyber physical systems
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
NoCAlert: An On-Line and Real-Time Fault Detection Mechanism for Network-on-Chip Architectures
MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
A fault tolerant NoC architecture using quad-spare mesh topology and dynamic reconfiguration
Journal of Systems Architecture: the EUROMICRO Journal
A NOC closed-loop performance monitor and adapter
Microprocessors & Microsystems
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As CMOS technology scales down into the deep-submicron (DSM) domain, devices and interconnects are subject to new types of malfunctions and failures that are harder to predict and avoid with the current system-on-chip (SoC) design methodologies. Relaxing the requirement of 100% correctness in operation drastically reduces the costs of design but, at the same time, requires SoCs be designed with some degree of system-level fault-tolerance. In this paper, we introduce a high-level model of DSM failure patterns and propose a new communication paradigm for SoCs, namely stochastic communication. Specifically, for a generic tile-based architecture, we propose a randomized algorithm which not only separates computation from communication, but also provides the required fault-tolerance to on-chip failures. This new technique is easy and cheap to implement in SoCs that integrate a large number of communicating IP cores.