ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
An adaptive low-power transmission scheme for on-chip networks
Proceedings of the 15th international symposium on System Synthesis
Interfacing Cores with On-chip Packet-Switched Networks
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Low Power Error Resilient Encoding for On-Chip Data Buses
Proceedings of the conference on Design, automation and test in Europe
Low-Latency Virtual-Channel Routers for On-Chip Networks
Proceedings of the 31st annual international symposium on Computer architecture
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A Heuristic for Peak Power Constrained Design of Network-on-Chip (NoC) Based Multimode Systems
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
A Quality-of-Service Mechanism for Interconnection Networks in System-on-Chips
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Towards on-chip fault-tolerant communication
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
An event-based network-on-chip monitoring service
HLDVT '04 Proceedings of the High-Level Design Validation and Test Workshop, 2004. Ninth IEEE International
Energy- and performance-aware mapping for regular NoC architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A robust protocol for concurrent on-line test (COLT) of NoC-based systems-on-a-chip
Proceedings of the 44th annual Design Automation Conference
SAPP: scalable and adaptable peak power management in nocs
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
PowerAntz: distributed power sharing strategy for network on chip
Proceedings of the 13th international symposium on Low power electronics and design
Robust concurrent online testing of network-on-chip-based SoCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A generic network interface architecture for a networked processor array (NePA)
ARCS'08 Proceedings of the 21st international conference on Architecture of computing systems
A distributed concurrent on-line test scheduling protocol for many-core NoC-based systems
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Network interface design based on mutual interface definition
International Journal of High Performance Systems Architecture
PowerAntz: Ant behavior inspired power budget distribution scheme for Network-on-Chip systems
Microelectronics Journal
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This paper proposes a Core Network Interface (CNI) architecture to interface IP cores with on-chip networks. Besides the basic functionality of packetizing communication requests and responses, we expect the CNI to provide additional services critical to communication in complex systems-on-a-chip (SoC). A CNI for interfacing with OCP-compliant core interfaces was developed for architecture validation. With the support of a modified on-chip router, the CNI was setup to bound on-chip communication latency jitter. We observed that jitter due to inefficient virtual channel allocation in a particular configuration of an on-chip interconnection network lead to latency variations of up to 400%. Using a class-based virtual channel allocation scheme in a 2D torus network, we provide for predictable end-to-end latency. While the proposed scheme does not guarantee least possible end-to-end latency, it provides for constrained bounds.