Core Network Interface Architecture and Latency Constrained On-Chip Communication
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
A robust protocol for concurrent on-line test (COLT) of NoC-based systems-on-a-chip
Proceedings of the 44th annual Design Automation Conference
SAPP: scalable and adaptable peak power management in nocs
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Robust concurrent online testing of network-on-chip-based SoCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Run-time task allocation considering user behavior in embedded multiprocessor networks-on-chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |
Designing NoC-based systems has become increasingly complex with support for multiple functionalities. Decisions regarding interconnections between the heterogeneous system components and routing of system communication affect system performance and power consumption. This research provides a heuristic to determine the neighborhood configuration for each component. By controlling the communication bandwidth allocation, simulation results with synthetic and real workloads indicate that our heuristic is able to control the peak power consumption, but at cost of throughput degradation.