A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Guest Editor's Introduction: What is Infrastructure IP?
IEEE Design & Test
A Set of Benchmarks fo Modular Testing of SOCs
ITC '02 Proceedings of the 2002 IEEE International Test Conference
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Exploiting an I-IP for In-Field SOC Test
DFT '04 Proceedings of the Defect and Fault Tolerance in VLSI Systems, 19th IEEE International Symposium
A Heuristic for Peak Power Constrained Design of Network-on-Chip (NoC) Based Multimode Systems
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Power-Aware Test Scheduling in Network-on-Chip Using Variable-Rate On-Chip Clocking
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Exploiting Structural Duplication for Lifetime Reliability Enhancement
Proceedings of the 32nd annual international symposium on Computer Architecture
Integrating BIST Techniques for On-Line SoC Testing
IOLTS '05 Proceedings of the 11th IEEE International On-Line Testing Symposium
Test Scheduling for Network-on-Chip with BIST and Precedence Constraints
ITC '04 Proceedings of the International Test Conference on International Test Conference
Energy-aware mapping for tile-based NoC architectures under performance constraints
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Core Network Interface Architecture and Latency Constrained On-Chip Communication
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
A TDM Test Scheduling Method for Network-on-Chip Systems
MTV '05 Proceedings of the Sixth International Workshop on Microprocessor Test and Verification
An Infrastructure IP for Online Testing of Network-on-Chip Based SoCs
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
A robust protocol for concurrent on-line test (COLT) of NoC-based systems-on-a-chip
Proceedings of the 44th annual Design Automation Conference
Indirect test architecture for SoC testing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Online traffic-aware fault detection for networks-on-chip
Journal of Parallel and Distributed Computing
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Lifetime concerns for complex systems-on-a-chip (SoC) designs due to decreasing levels in reliability motivate the development of solutions to ensure reliable operation. A precursor to any proposed recovery scheme would require the identification of failures in the system. Non-concurrent infield testing is an impractical solution due to prohibitive costs in terms of testpower and test time. This novel research proposes the use of concurrent online testing (COLT) to circumvent these issues. A test infrastructure-intellectual property (TI-IP) is deployed within network-on-chip (NoC)-based SoC designs to provide online test support while managing intrusion of test into executing applications within the system. This research describes the architecture and operation of a TI-IP capable of COLT. To address scalability of this solution, we show how these would operate when more than one is deployed in an SoC. In the absence of benchmarks for the analysis of COLT, two baseline and eight TI-IP configuration variations within SoC test configurations were developed using application and test benchmarks from the research domain. The power profiles from the NoCSim simulation environment are reported here demonstrating how different configurations of TI-IPs would operate. A robust TI-IP protocol is also specified and possible hazards and their mitigations are identified.