Proceedings of the conference on Design, automation and test in Europe: Proceedings
Robust concurrent online testing of network-on-chip-based SoCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An IEEE 1149.1-based BIST method for at-speed testing of inter-switch links in network on chip
Microelectronics Journal
A new test scheduling algorithm based on Networks-on-Chip as Test Access Mechanisms
Journal of Parallel and Distributed Computing
A fully parallel BIST-based method to test the crosstalk defects on the inter-switch links in NOC
Microelectronics Journal
Test pin count reduction for NoC-based test delivery in multicore SOCs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Hi-index | 0.00 |
Network-on-Chip is the new paradigm in core-based system design. Reuse of the on-chip communication network for NoC test is critical to reduce test cost. However, efficient reuse of the communication network for test of legacy cores is challenging. A mismatch between the NoC channel width and the core test wrapper width can adversely affect test efficiency. In addition, stringent power constraints on todayýs high-density systems exacerbate the test scheduling problem. In this paper, we propose a method for efficiently utilizing the on-chip network for power-aware test scheduling in NoCs. We make use of on-chip clocking to speed up test data transfer by selectively using faster clocks to test certain cores; other cores receive slower clocks to limit test power consumption. A novel method is presented to determine the clock rate distribution among cores. Experimental results for the ITCý02 benchmarks show that the new method leads to substantial reduction in overall test application time, while satisfying power constraints.