Global routing with crosstalk constraints
DAC '98 Proceedings of the 35th annual Design Automation Conference
Fault modeling and simulation for crosstalk in system-on-chip interconnects
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Interconnect tuning strategies for high-performance ICs
Proceedings of the conference on Design, automation and test in Europe
March tests for word-oriented memories
Proceedings of the conference on Design, automation and test in Europe
An on-chip march pattern generator for testing embedded memory cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Signal integrity fault analysis using reduced-order modeling
Proceedings of the 39th annual Design Automation Conference
Crosstalk Minimization in Three-Layer HVH Channel Routing
DFT '97 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems
A structured and scalable mechanism for test access to embedded reusable cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Solving capture in switched two-node Ethernets by changing only one node
LCN '95 Proceedings of the 20th Annual IEEE Conference on Local Computer Networks
Crosstalk Noise Verification in Digital Designs with Interconnect Process Variations
VLSID '01 Proceedings of the The 14th International Conference on VLSI Design (VLSID '01)
March LR: a test for realistic linked faults
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Testing SoC Interconnects for Signal Integrity Using Boundary Scan
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Analysis of Interconnect Crosstalk Defect Coverage of Test Sets
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Test Pattern Generation for Signal Integrity Faults on Long Interconnects
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Testing strategies for networks on chip
Networks on chip
Power-driven Design of Router Microarchitectures in On-chip Networks
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Extending JTAG for Testing Signal Integrity in SoCs
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Novel Algorithm for Testing Crosstalk Induced Delay Faults in VLSI Circuits
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
HERMES: an infrastructure for low area overhead packet-switching networks on chip
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
Power-Aware Test Scheduling in Network-on-Chip Using Variable-Rate On-Chip Clocking
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Design, Synthesis, and Test of Networks on Chips
IEEE Design & Test
Design and analysis of an NoC architecture from performance, reliability and energy perspective
Proceedings of the 2005 ACM symposium on Architecture for networking and communications systems
Reuse-based test access and integrated test scheduling for network-on-chip
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A concurrent testing method for NoC switches
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Exploring Fault-Tolerant Network-on-Chip Architectures
DSN '06 Proceedings of the International Conference on Dependable Systems and Networks
Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism
ETS '06 Proceedings of the Eleventh IEEE European Test Symposium
Using the inter- and intra-switch regularity in NoC switch testing
Proceedings of the conference on Design, automation and test in Europe
Toward a scalable test methodology for 2D-mesh Network-on-Chips
Proceedings of the conference on Design, automation and test in Europe
MDSI: Signal Integrity Interconnect Fault Modeling and Testing for SoCs
Journal of Electronic Testing: Theory and Applications
Online NoC Switch Fault Detection and Diagnosis Using a High Level Fault Model
DFT '07 Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Test Pattern Generation and Compaction for Crosstalk Induced Glitches and Delay Faults
VLSID '10 Proceedings of the 2010 23rd International Conference on VLSI Design
An IEEE 1149.1-based BIST method for at-speed testing of inter-switch links in network on chip
Microelectronics Journal
IEEE Transactions on Computers
Bringing communication networks on a chip: test and verification implications
IEEE Communications Magazine
Testing SoC interconnects for signal integrity using extended JTAG architecture
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Constraint-Driven Test Scheduling for NoC-Based Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Testing Network-on-Chip Communication Fabrics
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper we propose a BIST based method to test network on chip (NOC) communication infrastructure. The proposed method utilizes an IEEE 1149.1 architecture based on BIST to at-speed test of crosstalk faults for inter-switch links as well as an IEEE 1500-compliant wrapper to test switches themselves in NOC communication infrastructure. The former architecture includes enhanced cells intended for MAF model test patterns generation and analysis test responses, and the later architecture includes: (a) a March decoder which decodes and executes March commands, which are scanned in serially from input system, on First-In-First-Out (FIFO) buffers in the switch; and (b) a scan chain which is defined to test routing logic block of the switch. To at-speed test inter-switch links one new instruction is used to control cells and TPG controller. Two new instructions, as well as, are applied to activate March decoder and to control scan activities in switch test session. These instructions are defined to fully comply with conventional IEEE 1149.1 and IEEE 1500 standards.