IEEE Spectrum
Embedding infrastructure IP for SOC yield improvement
Proceedings of the 39th annual Design Automation Conference
A Complete Strategy for Testing an On-Chip Multiprocessor Architecture
IEEE Design & Test
A Study on Communication Issues for Systems-on-Chip
Proceedings of the 15th symposium on Integrated circuits and systems design
The Impact of NoC Reuse on the Testing of Core-based Systems
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Embedded Memory Test and Repair: Infrastructure IP for SOC Yield
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Logic BIST and Scan Test Techniques for Multiple Identical Blocks
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Testing strategies for networks on chip
Networks on chip
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Design, Synthesis, and Test of Networks on Chips
IEEE Design & Test
Methodologies and Algorithms for Testing Switch-Based NoC Interconnects
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Bringing communication networks on a chip: test and verification implications
IEEE Communications Magazine
Proceedings of the 6th FPGAworld Conference
An IEEE 1149.1-based BIST method for at-speed testing of inter-switch links in network on chip
Microelectronics Journal
A complete self-testing and self-configuring NoC infrastructure for cost-effective MPSoCs
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Wireless Health Systems, On-Chip and Off-Chip Network Architectures
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This paper presents a BIST strategy for testing the NoC interconnect network, and investigates if the strategy is a suitable approach for the task. All switches and links in the NoC are tested with BIST, running at full clock-speed, and in a functional-like mode. The BIST is carried out as a go/no-go BIST operation at start up, or on command. It is shown that the proposed methodology can be applied for different implementations of deflecting switches, and that the test time is limited to a few thousand-clock cycles with fault coverage close to 100%.