Fat-trees: universal networks for hardware-efficient supercomputing
IEEE Transactions on Computers
A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Addressing the system-on-a-chip interconnect woes through communication-based design
Proceedings of the 38th annual Design Automation Conference
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Parallel Computer Architecture: A Hardware/Software Approach
Parallel Computer Architecture: A Hardware/Software Approach
Networks on Silicon: Blessing or Nightmare?
DSD '02 Proceedings of the Euromicro Symposium on Digital Systems Design
Networks on Silicon: Combining Best-Effort and Guaranteed Services
Proceedings of the conference on Design, automation and test in Europe
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
The Nostrum Backbone - a Communication Protocol Stack for Networks on Chip
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Load Distribution with the Proximity Congestion Awareness in a Network on Chip
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
An Energy-Efficient Reconfigurable Circuit-Switched Network-on-Chip
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Quality-of-service and error control techniques for mesh-based network-on-chip architectures
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Fault tolerance overhead in network-on-chip flow control schemes
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Key research problems in NoC design: a holistic perspective
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Spatial division multiplexing: a novel approach for guaranteed throughput on NoCs
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Æthereal Network on Chip: Concepts, Architectures, and Implementations
IEEE Design & Test
Evaluation of on-chip networks using deflection routing
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
A hierarchical modeling framework for on-chip communication architectures of multiprocessing SoCs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Transaction-Based Communication-Centric Debug
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
A Generic Model for Formally Verifying NoC Communication Architectures: A Case Study
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
An Analytical Approach for Dimensioning Mixed Traffic Networks
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Toward a scalable test methodology for 2D-mesh Network-on-Chips
Proceedings of the conference on Design, automation and test in Europe
A scalable, timing-safe, network-on-chip architecture with an integrated clock distribution method
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
Analytical router modeling for networks-on-chip performance analysis
Proceedings of the conference on Design, automation and test in Europe
Voltage-frequency island partitioning for GALS-based networks-on-chip
Proceedings of the 44th annual Design Automation Conference
Introducing the SuperGT network-on-chip: SuperGT QoS: more than just GT
Proceedings of the 44th annual Design Automation Conference
Router architecture for high-performance NoCs
Proceedings of the 20th annual conference on Integrated circuits and systems design
NoC design flow for TDMA and QoS management in a GALS context
EURASIP Journal on Embedded Systems
Channel trees: reducing latency by sharing time slots in time-multiplexed networks on chip
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Analysis and optimization of prediction-based flow control in networks-on-chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Slot allocation using logical networks for TDM virtual-circuit configuration for network-on-chip
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Designing efficient irregular networks for heterogeneous systems-on-chip
Journal of Systems Architecture: the EUROMICRO Journal
Journal of Systems Architecture: the EUROMICRO Journal
Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Hardwired Networks on Chip in FPGAs to Unify Functional and Con?guration Interconnects
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Multicast parallel pipeline router architecture for network-on-chip
Proceedings of the conference on Design, automation and test in Europe
Reducing Packet Dropping in a Bufferless NoC
Euro-Par '08 Proceedings of the 14th international Euro-Par conference on Parallel Processing
Energy efficient streaming applications with guaranteed throughput on MPSoCs
EMSOFT '08 Proceedings of the 8th ACM international conference on Embedded software
Integration, the VLSI Journal
TDM virtual-circuit configuration for network-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On NoC Bandwidth Sharing for the Optimization of Area Cost and Test Application Time
IEICE - Transactions on Information and Systems
An architectural co-synthesis algorithm for energy-aware Network-on-Chip design
Journal of Systems Architecture: the EUROMICRO Journal
Synthesis of predictable networks-on-chip-based interconnect architectures for chip multiprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A case for bufferless routing in on-chip networks
Proceedings of the 36th annual international symposium on Computer architecture
REDEFINE: Runtime reconfigurable polymorphic ASIC
ACM Transactions on Embedded Computing Systems (TECS)
Design and management of voltage-frequency island partitioned networks-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SCARAB: a single cycle adaptive routing and bufferless network
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
A method for calculating hard QoS guarantees for Networks-on-Chip
Proceedings of the 2009 International Conference on Computer-Aided Design
Quality-of-service and error control techniques for mesh-based network-on-chip architectures
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Topology/floorplan/pipeline co-design of cascaded crossbar bus
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Communication modeling of multicast in all-port wormhole-routed NoCs
Journal of Systems and Software
Back Suction: Service Guarantees for Latency-Sensitive On-chip Networks
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Virtual point-to-point connections for NoCs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
The aethereal network on chip after ten years: goals, evolution, lessons, and future
Proceedings of the 47th Design Automation Conference
Application-aware NoC design for efficient SDRAM access
Proceedings of the 47th Design Automation Conference
aelite: a flit-synchronous network on chip with composable and predictable services
Proceedings of the Conference on Design, Automation and Test in Europe
Priority based forced requeue to reduce worst-case latencies for bursty traffic
Proceedings of the Conference on Design, Automation and Test in Europe
Adaptive and deadlock-free tree-based multicast routing for networks-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A worst case performance model for TDM virtual circuit in NoCs
NPC'10 Proceedings of the 2010 IFIP international conference on Network and parallel computing
Embedded network protocols for mobile devices
FMICS'10 Proceedings of the 15th international conference on Formal methods for industrial critical systems
An analytical approach for network-on-chip performance analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An improved algorithm for slot selection in the Æthereal network-on-chip
Proceedings of the Fifth International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip
LOFT: A High Performance Network-on-Chip Providing Quality-of-Service Support
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
Adaptive Flow Control for Robust Performance and Energy
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
Reliability analysis of on-chip communication architectures: An MPEG-2 video decoder case study
Microprocessors & Microsystems
A TDM slot allocation flow based on multipath routing in NoCs
Microprocessors & Microsystems
Power-efficient tree-based multicast support for networks-on-chip
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Microprocessors & Microsystems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal of Parallel and Distributed Computing
CoQoS: Coordinating QoS-aware shared resources in NoC-based SoCs
Journal of Parallel and Distributed Computing
Low-energy GALS NoC with FIFO-Monitoring dynamic voltage scaling
Microelectronics Journal
Cross clock-domain TDM virtual circuits for networks on chips
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Real-time communication analysis for networks with two-stage arbitration
EMSOFT '11 Proceedings of the ninth ACM international conference on Embedded software
The ReNoC Reconfigurable Network-on-Chip: Architecture, Configuration Algorithms, and Evaluation
ACM Transactions on Embedded Computing Systems (TECS)
Networks on chips: structure and design methodologies
Journal of Electrical and Computer Engineering - Special issue on Networks-on-Chip: Architectures, Design Methodologies, and Case Studies
High-throughput differentiated service provision router architecture for wireless network-on-chip
International Journal of High Performance Systems Architecture
Design and evaluation of Mesh-of-Tree based Network-on-Chip using virtual channel router
Microprocessors & Microsystems
Dynamic QoS management for chip multiprocessors
ACM Transactions on Architecture and Code Optimization (TACO)
Globally Synchronized Frames for guaranteed quality-of-service in on-chip networks
Journal of Parallel and Distributed Computing
Designing best effort networks-on-chip to meet hard latency constraints
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Wireless Health Systems, On-Chip and Off-Chip Network Architectures
A TDM NoC supporting QoS, multicast, and fast connection set-up
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Parallel probing: dynamic and constant time setup procedure in circuit switching NoC
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Adaptive virtual channel partitioning for network-on-chip in heterogeneous architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
Journal of Systems Architecture: the EUROMICRO Journal
Microprocessors & Microsystems
Providing multiple hard latency and throughput guarantees for packet switching networks on chip
Computers and Electrical Engineering
Microprocessors & Microsystems
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In today's emerging Network-on-Chips, there is a need for different traffic classes with different Quality-of-Service guarantees. Within our NoC architecture Nostrum, we have implemented a service of Guaranteed Bandwidth (GB), and latency, in addition to the already existing service of Best-Effort (BE) packet delivery. The guaranteed bandwidth is accessed via Virtual Circuits (VC). The VCs are implemented using a combination of two concepts that we call Looped Containers' and Temporally Disjoint Networks'. The Looped Containers are used to guarantee access to the network -- independently of the current network load without dropping packets; and the TDNs are used in order to achieve several VCs, plus ordinary BE traffic, in the network. The TDNs are a consequence of the deffective routing policy used, and gives rise to an explicit time-division-multiplexing within the network. To prove our concept an HDL implementation has been synthesised and simulated. The cost in terms of additional hardware needed, as well as additional bandwidth is very low -- less than 2 percent in both cases! Simulations showed that ordinary BE traffic is practically unaffected by the VCs.