A comprehensive analytical model for wormhole routing in multicomputer systems
Journal of Parallel and Distributed Computing
Efficient multicast in all-port wormhole-routed hypercubes
Journal of Parallel and Distributed Computing
A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Powering networks on chips: energy-efficient and reliable interconnect design for SoCs
Proceedings of the 14th international symposium on Systems synthesis
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
Optimal software multicast in wormhole-routed multistage networks
Proceedings of the 1994 ACM/IEEE conference on Supercomputing
Multidestination Message Passing Mechanism Conforming to Base Wormhole Routing Scheme
PCRCW '94 Proceedings of the First International Workshop on Parallel Computer Routing and Communication
A Performance Model of Broadcast Communication in Wormhole-Routed Hypercubes
MASCOTS '00 Proceedings of the 8th International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems
An analytical model of wormhole-routed hypercubes under broadcast traffic
Performance Evaluation
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Interconnect intellectual property for network-on-chip (NoC)
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
QNoC: QoS architecture and design process for network on chip
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Key research problems in NoC design: a holistic perspective
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Æthereal Network on Chip: Concepts, Architectures, and Implementations
IEEE Design & Test
Connection-oriented Multicasting in Wormhole-switched Networks on Chip
ISVLSI '06 Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
An Analytical Performance Model for the Spidergon NoC
AINA '07 Proceedings of the 21st International Conference on Advanced Networking and Applications
Multicast parallel pipeline router architecture for network-on-chip
Proceedings of the conference on Design, automation and test in Europe
A Performance Model of Communication in the Quarc NoC
ICPADS '08 Proceedings of the 2008 14th IEEE International Conference on Parallel and Distributed Systems
Quarc: A Novel Network-On-Chip Architecture
ICPADS '08 Proceedings of the 2008 14th IEEE International Conference on Parallel and Distributed Systems
A performance model of multicast communication in wormhole-routed networks on-chip
IPDPS '09 Proceedings of the 2009 IEEE International Symposium on Parallel&Distributed Processing
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Multicast is one of the most frequently used collective communication operations in multi-core SoC platforms. Bus as the traditional interconnect architecture for SoC development has been highly efficient in delivering multicast messages. Since the bus is non-scalable, it can not address the bandwidth requirements of the large SoCs. The networks on-chip (NoCs) emerged as a scalable alternative to address the increasing communication demands of such systems. However, due to its hop-to-hop communication, the NoCs may not be able to deliver multicast operations as efficiently as buses do. Adopting multi-port routers has been an approach to improve the performance of the multicast operations in interconnection networks. This paper presents a novel analytical model to compute communication latency of the multicast operation in wormhole-routed interconnection networks employing asynchronous multi-port routers scheme. The model is applied to the Quarc NoC and its validity is verified by comparing the model predictions against the results obtained from a discrete-event simulator developed using OMNET++.