Analytical modeling and evaluation of On-Chip Interconnects using Network Calculus
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Power optimization for application-specific networks-on-chips: A topology-based approach
Microprocessors & Microsystems
Evaluating the energy consumption and the silicon area of on-chip interconnect architectures
Journal of Systems Architecture: the EUROMICRO Journal
An analytical performance model for the Spidergon NoC with virtual channels
Journal of Systems Architecture: the EUROMICRO Journal
Communication modeling of multicast in all-port wormhole-routed NoCs
Journal of Systems and Software
Evolutionary-based conflict-free scheduling of collective communications on spidergon NoCs
Proceedings of the 12th annual conference on Genetic and evolutionary computation
aEqualized: a novel routing algorithm for the Spidergon network on chip
Proceedings of the Conference on Design, Automation and Test in Europe
An analytical model of broadcast in QoS-aware wormhole-routed NoCs
Journal of Systems and Software
Static timing analysis for modeling QoS in networks-on-chip
Journal of Parallel and Distributed Computing
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
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Networks on chip (NoC) emerged as a promising alternative to bus-based interconnect networks to handle the increasing communication requirements of the large systems on chip. Employing an appropriate topology for a NoC is of high importance mainly because it typically trade-offs between cross-cutting concerns such as performance and cost. The spidergon topology is a novel architecture which is proposed recently for NoC domain. The objective of the spidergon NoC has been addressing the need for a fixed and optimized topology to realize cost effective multi-processor SoC (MPSoC) development [7]. In this paper we analyze the traffic behavior in the spidergon scheme and present an analytical evaluation of the average message latency in the architecture. We prove the validity of the analysis by comparing the model against the results produced by a discreteevent simulator.