Embedding trees in massively parallel computers
Journal of Systems Architecture: the EUROMICRO Journal
Latency-rate servers: a general model for analysis of traffic scheduling algorithms
IEEE/ACM Transactions on Networking (TON)
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Traffic analysis for on-chip networks design of multimedia applications
Proceedings of the 39th annual Design Automation Conference
Embedded Software in Network Processors - Models and Algorithms
EMSOFT '01 Proceedings of the First International Workshop on Embedded Software
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
IEEE Transactions on Computers
Key research problems in NoC design: a holistic perspective
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Design and analysis of an NoC architecture from performance, reliability and energy perspective
Proceedings of the 2005 ACM symposium on Architecture for networking and communications systems
System architecture evaluation using modular performance analysis: a case study
International Journal on Software Tools for Technology Transfer (STTT)
An Analytical Performance Model for the Spidergon NoC
AINA '07 Proceedings of the 21st International Conference on Advanced Networking and Applications
Analytical router modeling for networks-on-chip performance analysis
Proceedings of the conference on Design, automation and test in Europe
Service-Oriented Network Description and Discovery for High-Performance
SOCA '07 Proceedings of the IEEE International Conference on Service-Oriented Computing and Applications
Applying Dataflow Analysis to Dimension Buffers for Guaranteed Performance in Networks on Chip
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Optimal routing for end-to-end guarantees using Network Calculus
Performance Evaluation
Network calculus: a theory of deterministic queuing systems for the internet
Network calculus: a theory of deterministic queuing systems for the internet
Static timing analysis for modeling QoS in networks-on-chip
Journal of Parallel and Distributed Computing
Delay analysis of wormhole based heterogeneous NoC
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Analytical modeling for multi-transaction bus on distributed systems
ICA3PP'12 Proceedings of the 12th international conference on Algorithms and Architectures for Parallel Processing - Volume Part II
Proceedings of the International Conference on Computer-Aided Design
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Network-on-Chip (NoC) has been proposed as an alternative to bus-based schemes to achieve high performance and scalability in System-on-Chip (SoC) design. Performance evaluation of On-Chip Interconnect (OCI) architectures is widely based on simulation which becomes computationally expensive, especially for large-scale NoCs. In this paper, a performance analysis model using Network Calculus is presented to characterize and evaluate the performance of NoC-based applications. The 2D Mesh on-chip interconnect is analyzed and main performance metrics such as end-to-end delay and buffer size requirements are computed and compared against the results produced by a discrete event simulator. The results shed more light on the potential of this analytical technique as a useful tool for NoC design and performance analysis.