Experimental analysis of the fastest optimum cycle ratio and mean algorithms
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Æthereal Network on Chip: Concepts, Architectures, and Implementations
IEEE Design & Test
Models of Computation for Networks on Chip
ACSD '06 Proceedings of the Sixth International Conference on Application of Concurrency to System Design
A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Modelling run-time arbitration by latency-rate servers in dataflow graphs
SCOPES '07 Proceedingsof the 10th international workshop on Software & compilers for embedded systems
Efficient computation of buffer capacities for cyclo-static dataflow graphs
Proceedings of the 44th annual Design Automation Conference
IEEE Transactions on Signal Processing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
CoMPSoC: A template for composable and predictable multi-processor system on chips
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Analytical modeling and evaluation of On-Chip Interconnects using Network Calculus
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Analytical performance modeling of shuffle-exchange inspired mesh-based Network-on-Chips
Performance Evaluation
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A Network on Chip (NoC) with end-to-end flow control is modelled by a cyclo-static dataflow graph. Using the proposed model together with state-of-the-art dataflow analysis algorithms, we size the buffers in the network interfaces. We show, for a range of NoC designs, that buffer sizes are determined with a run time comparable to existing analytical methods, and results comparable to exhaustive simulation.