Fundamentals of queueing theory (2nd ed.).
Fundamentals of queueing theory (2nd ed.).
Addressing the system-on-a-chip interconnect woes through communication-based design
Proceedings of the 38th annual Design Automation Conference
Software Synthesis from Dataflow Graphs
Software Synthesis from Dataflow Graphs
On the Quantitative Specification of Jitter Constrained Periodic Streams
MASCOTS '97 Proceedings of the 5th International Workshop on Modeling, Analysis, and Simulation of Computer and Telecommunications Systems
aSOC: A Scalable, Single-Chip Communications Architecture
PACT '00 Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques
Statistical characteristics and multiplexing of MPEG streams
INFOCOM '95 Proceedings of the Fourteenth Annual Joint Conference of the IEEE Computer and Communication Societies (Vol. 2)-Volume - Volume 2
Task-level timing models for guaranteed performance in multiprocessor networks-on-chip
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
Proceedings of the conference on Design, automation and test in Europe - Volume 2
An Application-Specific Design Methodology for STbus Crossbar Generation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Minimising buffer requirements of synchronous dataflow graphs with model checking
Proceedings of the 42nd annual Design Automation Conference
A unified approach to constrained mapping and routing on network-on-chip architectures
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Æthereal Network on Chip: Concepts, Architectures, and Implementations
IEEE Design & Test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Access Regulation to Hot-Modules in Wormhole NoCs
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Buffer sizing for QoS flows in wormhole packet switching NoCs
Proceedings of the 20th annual conference on Integrated circuits and systems design
Channel trees: reducing latency by sharing time slots in time-multiplexed networks on chip
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Hardwired Networks on Chip in FPGAs to Unify Functional and Con?guration Interconnects
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Applying Dataflow Analysis to Dimension Buffers for Guaranteed Performance in Networks on Chip
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Highly-cited ideas in system codesign and synthesis
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
CoMPSoC: A template for composable and predictable multi-processor system on chips
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Application-specific networks-on-chip topology customization using network partitioning
IFMT '08 Proceedings of the 1st international forum on Next-generation multicore/manycore technologies
Node resource management for DSP applications on 3D network-on-chip architecture
DSP'09 Proceedings of the 16th international conference on Digital Signal Processing
A worst case performance model for TDM virtual circuit in NoCs
NPC'10 Proceedings of the 2010 IFIP international conference on Network and parallel computing
Application-specific temperature reduction systematic methodology for 2d and 3d networks-on-chip
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
A buffer-sizing algorithm for network-on-chips with multiple voltage-frequency Islands
Journal of Electrical and Computer Engineering - Special issue on Networks-on-Chip: Architectures, Design Methodologies, and Case Studies
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When designing a System-on-Chip (SoC) using a Network-on-Chip (NoC), silicon area and power consumption are two key elements to optimize. A dominant part of the NoC area and power consumption is due to the buffers in the Network Interfaces (NIs) needed to decouple computation from communication. Having such a decoupling prevents stalling of IP blocks due to the communication interconnect. The size of these buffers is especially important in real-time systems, as there they should be big enoughto obtain predictable performance. To ensure that buffers do not overflow, end-to-end flow-control is needed. One form of end-to-end flow-control used in NoCs is credit-based flow-control. This form places additional requirements on the buffer sizes, because the flow-control delays need to be taken into account. In this work, we present an algorithm to find the minimal decoupling buffer sizes for a NoC using TDMA and credit-based end-to-end flow-control, subject to the performance constraints of the applications running on the SoC. Our experiments show that our method results in a 84% reduction of the total NoC buffer area when compared to the state-of-the art buffer-sizing methods. Moreover, our method has a low run-time complexity, producing results in the order of minutes for our experiments, enabling quick design cycles for large SoC designs. Finally, our method can take into account multiple usecases running on the same SoC.