Nonuniform traffic spots (NUTS) in multistage interconnection networks
Journal of Parallel and Distributed Computing
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Viper: A Multiprocessor SOC for Advanced Set-Top Box and Digital TV Systems
IEEE Design & Test
Integrated Admission and Congestion Control for QoS Support in Clusters
CLUSTER '02 Proceedings of the IEEE International Conference on Cluster Computing
Global Reactive Congestion Control in Multicomputer Networks
HIPC '98 Proceedings of the Fifth International Conference on High Performance Computing
QNoC: QoS architecture and design process for network on chip
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip
IEEE Transactions on Parallel and Distributed Systems
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
HERMES: an infrastructure for low area overhead packet-switching networks on chip
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
Centralized end-to-end flow control in a best-effort network-on-chip
Proceedings of the 5th ACM international conference on Embedded software
Æthereal Network on Chip: Concepts, Architectures, and Implementations
IEEE Design & Test
Efficient link capacity and QoS design for network-on-chip
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A methodology for mapping multiple use-cases onto networks on chips
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Prediction-based flow control for network-on-chip traffic
Proceedings of the 43rd annual Design Automation Conference
A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Flow-aware allocation for on-chip networks
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
A Token-Managed Admission Control System for QoS Provision on a Best-Effort GALS Interconnect
Fundamenta Informaticae - Application of Concurrency to System Design
HOPE: hotspot congestion control for Clos network on chip
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
A Token-Managed Admission Control System for QoS Provision on a Best-Effort GALS Interconnect
Fundamenta Informaticae - Application of Concurrency to System Design
A distributed interleaving scheme for efficient access to WideIO DRAM memory
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Gana: A novel low-cost conflict-free NoC architecture
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Wireless Health Systems, On-Chip and Off-Chip Network Architectures
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Network on Chip (NoC) may be the primary interconnect mechanism for future Systems-on-Chip (SoC). Real-life SoCs typically include hot-modules such as DRAM controller or floating point unit, which are bandwidth limited and in high demand by other units. In this paper we demonstrate that the mere existence of one or more hot-modules in a wormhole-based NoC dramatically reduces network efficiency and causes an unfair allocation of system resources. We demonstrate that a single hot-module destroys the performance of the entire SoC, even if network resources are over-provisioned. In order to resolve the hot-module effect, we introduce a novel low-cost credit based distributed access regulation technique that fairly allocates access rights to the hot-module. Unlike other methods, this technique directly addresses the root cause of network buffer congestion phenomena. Using simulation, we show the effectiveness of the suggested mechanism in various NoC scenarios.