A methodology for mapping multiple use-cases onto networks on chips

Authors:
Srinivasan Murali;Martijn Coenen;Andrei Radulescu;Kees Goossens;Giovanni De Micheli
Affiliations:
Stanford University, Stanford;Philips Research Laboratories, The Netherlands;Philips Research Laboratories, The Netherlands;Philips Research Laboratories, The Netherlands;LSI, EPFL, Switzerland
Venue:
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Year:
2006

Citing 21
Cited 39

A generic architecture for on-chip packet-switched interconnections

DATE '00 Proceedings of the conference on Design, automation and test in Europe
Addressing the system-on-a-chip interconnect woes through communication-based design

Proceedings of the 38th annual Design Automation Conference
Micronetwork-based integration for SOCs: 673

Proceedings of the 38th annual Design Automation Conference
On-chip communication architecture for OC-768 network processors

Proceedings of the 38th annual Design Automation Conference
Route packets, not wires: on-chip inteconnection networks

Proceedings of the 38th annual Design Automation Conference
Constraint-driven communication synthesis

Proceedings of the 39th annual Design Automation Conference
Networks on Chips: A New SoC Paradigm

Computer
Viper: A Multiprocessor SOC for Advanced Set-Top Box and Digital TV Systems

IEEE Design & Test
Networks on chip

Networks on chip
Efficient Synthesis of Networks On Chip

ICCD '03 Proceedings of the 21st International Conference on Computer Design
xpipes: a Latency Insensitive Parameterized Network-on-chip Architecture For Multi-Processor SoCs

ICCD '03 Proceedings of the 21st International Conference on Computer Design
Bandwidth-Constrained Mapping of Cores onto NoC Architectures

Proceedings of the conference on Design, automation and test in Europe - Volume 2
SUNMAP: a tool for automatic topology selection and generation for NoCs

Proceedings of the 41st annual Design Automation Conference
Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip

DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures

DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip

IEEE Transactions on Parallel and Distributed Systems
A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification

Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
A unified approach to constrained mapping and routing on network-on-chip architectures

CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Mapping and configuration methods for multi-use-case networks on chips

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Energy-aware mapping for tile-based NoC architectures under performance constraints

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees

Proceedings of the 2005 Asia and South Pacific Design Automation Conference

Networks on chips for high-end consumer-electronics TV system architectures

Proceedings of the conference on Design, automation and test in Europe: Designers' forum
Designing application-specific networks on chips with floorplan information

Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Access Regulation to Hot-Modules in Wormhole NoCs

NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
NoC Design and Implementation in 65nm Technology

NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Interactive presentation: Capturing the interaction of the communication, memory and I/O subsystems in memory-centric industrial MPSoC platforms

Proceedings of the conference on Design, automation and test in Europe
Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip

Proceedings of the conference on Design, automation and test in Europe
Multiprocessor systems synthesis for multiple use-cases of multiple applications on FPGA

ACM Transactions on Design Automation of Electronic Systems (TODAES)
A monitoring-aware network-on-chip design flow

Journal of Systems Architecture: the EUROMICRO Journal
Resource-efficient routing and scheduling of time-constrained streaming communication on networks-on-chip

Journal of Systems Architecture: the EUROMICRO Journal
Scenario selection and prediction for DVS-aware scheduling of multimedia applications

Journal of Signal Processing Systems - Special Issue: Embedded computing systems for DSP
Statistical Approach to NoC Design

NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
User-aware dynamic task allocation in networks-on-chip

Proceedings of the conference on Design, automation and test in Europe
System-scenario-based design of dynamic embedded systems

ACM Transactions on Design Automation of Electronic Systems (TODAES)
A topology design customization approach for STNoC

Proceedings of the 2nd international conference on Nano-Networks
Resource Management Policy Handling Multiple Use-Cases in MPSoC Platforms Using Constraint Programming

ICLP '08 Proceedings of the 24th International Conference on Logic Programming
Dynamically reconfigurable on-chip communication architectures for multi use-case chip multiprocessor applications

Proceedings of the 2009 Asia and South Pacific Design Automation Conference
A methodology for application-specific NoC architecture generation in a dynamic task structure environment

Proceedings of the 19th ACM Great Lakes symposium on VLSI
Synthesis of predictable networks-on-chip-based interconnect architectures for chip multiprocessors

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Best of both worlds: A bus enhanced NoC (BENoC)

NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems

CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Evaluation of static and dynamic task mapping algorithms in NoC-based MPSoCs

SOC'09 Proceedings of the 11th international conference on System-on-chip
Communication-aware heuristics for run-time task mapping on NoC-based MPSoC platforms

Journal of Systems Architecture: the EUROMICRO Journal
Distributed Sequencing for Resource Sharing in Multi-applicative Heterogeneous NoC Platforms

NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Designing heterogeneous embedded network-on-chip platforms with users in mind

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Leveraging application-level requirements in the design of a NoC for a 4G SoC: a case study

Proceedings of the Conference on Design, Automation and Test in Europe
Online adaptation policy design for grid sensor networks with reconfigurable embedded nodes

Proceedings of the Conference on Design, Automation and Test in Europe
Exploring programming model-driven QoS support for NoC-based platforms

CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A holistic approach to network-on-chip synthesis

CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Capacity optimized NoC for multi-mode SoC

Proceedings of the 48th Design Automation Conference
Enhancing the security of time-division-multiplexing networks-on-chip through the use of multipath routing

Proceedings of the 4th International Workshop on Network on Chip Architectures
A dynamically reconfigurable communication architecture for multicore embedded systems

Journal of Systems Architecture: the EUROMICRO Journal
A buffer-sizing algorithm for network-on-chips with multiple voltage-frequency Islands

Journal of Electrical and Computer Engineering - Special issue on Networks-on-Chip: Architectures, Design Methodologies, and Case Studies
MpAssign: A Framework for Solving the Many-Core Platform Mapping Problem

Software—Practice & Experience
Efficient genetic based topological mapping using analytical models for on-chip networks

Journal of Computer and System Sciences
Mapping on multi/many-core systems: survey of current and emerging trends

Proceedings of the 50th Annual Design Automation Conference
An integrated, programming model-driven framework for NoC-QoS support in cluster-based embedded many-cores

Parallel Computing
Auto-design systematic methodology of cluster MPSoC for multiple concurrent applications

International Journal of Computer Applications in Technology
Bi-LCQ: A low-weight clustering-based Q-learning approach for NoCs

Microprocessors & Microsystems

Quantified Score

Hi-index	0.00

Visualization

Abstract

A communication-centric design approach, Networks on Chips (NoCs), has emerged as the design paradigm for designing a scalable communication infrastructure for future Systems on Chips (SoCs). As technology advances, the number of applications or use-cases integrated on a single chip increases rapidly. The different use-cases of the SoC have different communication requirements (such as different bandwidth, latency constraints) and traffic patterns. The underlying NoC architecture has to satisfy the constraints of all the use-cases. In this work, we present a methodology to map multiple use-cases onto the NoC architecture, satisfying the constraints of each use-case. We present dynamic re-configuration mechanisms that match the NoC configuration to the communication characteristics of each use-case, also accounting for use-cases that can run in parallel. The methodology is applied to several real and synthetic SoC benchmarks, which result in a large reduction in NoC area (an average of 80%) and power consumption (an average of 54%) compared to traditional design approaches.