Steady-state simulation of queueing processes: survey of problems and solutions
ACM Computing Surveys (CSUR)
A comprehensive analytical model for wormhole routing in multicomputer systems
Journal of Parallel and Distributed Computing
An architectural co-synthesis algorithm for distributed, embedded computing systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Orion: a power-performance simulator for interconnection networks
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
High-speed local area networks using wormhole routing: modeling and extensions
High-speed local area networks using wormhole routing: modeling and extensions
A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture
DSD '03 Proceedings of the Euromicro Symposium on Digital Systems Design
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Multi-objective mapping for mesh-based NoC architectures
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Thermal-Aware IP Virtualization and Placement for Networks-on-Chip Architecture
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
IEEE Transactions on Computers
A technique for low energy mapping and routing in network-on-chip architectures
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
A unified approach to constrained mapping and routing on network-on-chip architectures
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Energy-aware mapping for tile-based NoC architectures under performance constraints
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
A methodology for mapping multiple use-cases onto networks on chips
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
Design tradeoffs for tiled CMP on-chip networks
Proceedings of the 20th annual international conference on Supercomputing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Virtual Channels Planning for Networks-on-Chip
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Analytical router modeling for networks-on-chip performance analysis
Proceedings of the conference on Design, automation and test in Europe
IEEE Micro
A Markovian Performance Model for Networks-on-Chip
PDP '08 Proceedings of the 16th Euromicro Conference on Parallel, Distributed and Network-Based Processing (PDP 2008)
A comprehensive power-performance model for NoCs with multi-flit channel buffers
Proceedings of the 23rd international conference on Supercomputing
A multi-objective strategy for concurrent mapping and routing in networks on chip
IPDPS '09 Proceedings of the 2009 IEEE International Symposium on Parallel&Distributed Processing
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A method for calculating hard QoS guarantees for Networks-on-Chip
Proceedings of the 2009 International Conference on Computer-Aided Design
A3MAP: architecture-aware analytic mapping for networks-on-chip
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
"It's a small world after all": noc performance optimization via long-range link insertion
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A fast and elitist multiobjective genetic algorithm: NSGA-II
IEEE Transactions on Evolutionary Computation
Energy- and performance-aware mapping for regular NoC architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hi-index | 0.00 |
Network-on-Chips are now the popular communication medium to support inter-IP communications in complex on-chip systems with tens to hundreds IP cores. Higher scalability (compared to the traditional shared bus and point-to-point interconnects), throughput, and reliability are among the most important advantages of NoCs. Moreover, NoCs can well match current CAD methodologies mainly relying on modular and reusable structures with regularity of structural pattern. However, since NoCs are resource-limited, determining how to distribute application load over limited on-chip resources (e.g. switches, buffers, virtual channels, and wires) in order to improve the metrics of interest and satisfy the application requirements becomes a challenging research issue known as topological mapping problem. This paper introduces a topological mapping strategy for direct networks. The Multi-Objective Genetic Algorithm (MOGA) is used to obtain optimal Pareto-front of topological mapping solutions for an arbitrary network topology using a deadlock-free routing algorithm. Considered cost functions are the network latency and power consumption which are accurately estimated through two accurate analytical models. Before using the proposed analytical models in our MOGA method, we validate them through extensive simulation experiments, and compare their accuracy to some known models already proposed in the literature. We then quantitatively and qualitatively compare our analytical model based mapping method to two other methods: a genetic-based and a heuristic. Experimental evaluations using real workloads confirm that the proposed method is cost-efficient and can be used as a powerful tool for NoC design space exploration. Compared to the traditional mapping strategies, our mapping mechanism has the following advantages: (1) it greatly shortens the design period by using analytical models for fast and accurate predictions; (2) it can give a set of solutions, using MOGA, in terms of Pareto-front including, at least one performance-optimal and one power-optimal, and some intermediate solutions; and (3) its runtime is reduced by determining the best generation size based on the used benchmark.