Steady-state simulation of queueing processes: survey of problems and solutions
ACM Computing Surveys (CSUR)
Performance Analysis of k-ary n-cube Interconnection Networks
IEEE Transactions on Computers
A comprehensive analytical model for wormhole routing in multicomputer systems
Journal of Parallel and Distributed Computing
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Analytical Modeling of Wormhole-Routed k-Ary n-Cubes in the Presence of Hot-Spot Traffic
IEEE Transactions on Computers
Analysis of power consumption on switch fabrics in network routers
Proceedings of the 39th annual Design Automation Conference
Orion: a power-performance simulator for interconnection networks
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
SUNMAP: a tool for automatic topology selection and generation for NoCs
Proceedings of the 41st annual Design Automation Conference
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip
IEEE Transactions on Parallel and Distributed Systems
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
IEEE Transactions on Computers
Key research problems in NoC design: a holistic perspective
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Virtual Channels Planning for Networks-on-Chip
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Analytical router modeling for networks-on-chip performance analysis
Proceedings of the conference on Design, automation and test in Europe
Energy- and performance-aware mapping for regular NoC architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
System-Level Buffer Allocation for Application-Specific Networks-on-Chip Router Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Performance modeling of n-dimensional mesh networks
Performance Evaluation
Power-performance analysis of networks-on-chip with arbitrary buffer allocation schemes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
An analytical network performance model for SIMD processor CSX600 interconnects
Journal of Systems Architecture: the EUROMICRO Journal
Modeling the effects of hot-spot traffic load on the performance of wormhole-switched hypermeshes
Computers and Electrical Engineering
Efficient genetic based topological mapping using analytical models for on-chip networks
Journal of Computer and System Sciences
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Large Multi-Processor Systems-on-Chip use Networks-on-Chip with a high degree of reusability and scalability for message communication. Therefore, network infrastructure is a crucial element affecting the overall system performance. On the other hand, technology improvements may lead to much energy consumption in micro-routers of an on-chip network. This necessitates an exhaustive analysis of NoCs for future designs. This paper presents a comprehensive analytical model to predict message latency for different data flows traversing across the network. This model considers channel buffers of multiple flits which were not previously studied in NoC context. Also, architectural descriptions of the overall consumed power in the network components are extracted considering message arrival and service rates. The results obtained from simulation experiments confirm that the proposed performance and power models exhibit good accuracy for various network configurations and workloads.