On-chip communication architecture exploration: A quantitative evaluation of point-to-point, bus, and network-on-chip approaches

Authors:
Hyung Gyu Lee;Naehyuck Chang;Umit Y. Ogras;Radu Marculescu
Affiliations:
Seoul National University, Seoul, Korea;Seoul National University, Seoul, Korea;Carnegie Mellon University, Pittsburgh, PA;Carnegie Mellon University, Pittsburgh, PA
Venue:
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Year:
2008

Citing 18
Cited 38

Route packets, not wires: on-chip inteconnection networks

Proceedings of the 38th annual Design Automation Conference
Analysis of power consumption on switch fabrics in network routers

Proceedings of the 39th annual Design Automation Conference
Interconnection Networks: An Engineering Approach

Interconnection Networks: An Engineering Approach
Networks on Chips: A New SoC Paradigm

Computer
Orion: a power-performance simulator for interconnection networks

Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
System-Level Point-to-Point Communication Synthesis Using Floorplanning Information

ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Networks on chip

Networks on chip
A Case Study in Networks-on-Chip Design for Embedded Video

Proceedings of the conference on Design, automation and test in Europe - Volume 2
On-chip traffic modeling and synthesis for MPEG-2 video applications

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Micro-Network for SoC: Implementation of a 32-Port SPIN network

DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
An architecture and compiler for scalable on-chip communication

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Linear Programming based Techniques for Synthesis of Network-on-Chip Architectures

ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Energy- and Performance-Driven NoC Communication Architecture Synthesis Using a Decomposition Approach

Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Cycle-Accurate Energy Measurement and Characterization of FPGAs

Analog Integrated Circuits and Signal Processing
Cost considerations in network on chip

Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
Key research problems in NoC design: a holistic perspective

CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Mapping and configuration methods for multi-use-case networks on chips

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Energy- and performance-aware mapping for regular NoC architectures

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Voltage-frequency island partitioning for GALS-based networks-on-chip

Proceedings of the 44th annual Design Automation Conference
Analysis and optimization of prediction-based flow control in networks-on-chip

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Challenges and Promising Results in NoC Prototyping Using FPGAs

IEEE Micro
Invited paper: Network-on-Chip design and synthesis outlook

Integration, the VLSI Journal
Variation-adaptive feedback control for networks-on-chip with multiple clock domains

Proceedings of the 45th annual Design Automation Conference
Stream Transfer Balancing Scheme Utilizing Multi-path Routing in Networks on Chip

ARC '08 Proceedings of the 4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
Heuristics Core Mapping in On-Chip Networks for Parallel Stream-Based Applications

ICCS '08 Proceedings of the 8th international conference on Computational Science, Part I
MC-Sim: an efficient simulation tool for MPSoC designs

Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A comprehensive power-performance model for NoCs with multi-flit channel buffers

Proceedings of the 23rd international conference on Supercomputing
Lossless and Near-Lossless Image Compression Scheme Utilizing Blending-Prediction-Based Approach

ICCVG 2008 Proceedings of the International Conference on Computer Vision and Graphics: Revised Papers
Performance and power efficient on-chip communication using adaptive virtual point-to-point connections

NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
BiNoC: A bidirectional NoC architecture with dynamic self-reconfigurable channel

NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Design and management of voltage-frequency island partitioned networks-on-chip

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A system-level design methodology for application-specific networks-on-chip

Journal of Embedded Computing - PATMOS 2007 selected papers on low power electronics
Virtual point-to-point connections for NoCs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
Motion estimation and CABAC VLSI co-processors for real-time high-quality H.264/AVC video coding

Microprocessors & Microsystems
Priority-based packet communication on a bus-shaped structure for FPGA-systems

Proceedings of the Conference on Design, Automation and Test in Europe
Power-performance analysis of networks-on-chip with arbitrary buffer allocation schemes

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
Convex-based DOR routing for virtualization of NoC

NPC'10 Proceedings of the 2010 IFIP international conference on Network and parallel computing
A deadlock-free routing algorithm for dynamically reconfigurable Networks-on-Chip

Microprocessors & Microsystems
Reliability analysis of on-chip communication architectures: An MPEG-2 video decoder case study

Microprocessors & Microsystems
GNLS: a hybrid on-chip communication architecture for SoC designs

International Journal of High Performance Systems Architecture
Virtual path implementation of multi-stream routing in network on chip

PaCT'11 Proceedings of the 11th international conference on Parallel computing technologies
A Torus-Based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Automatic adjustment of a medical imaging data acquisition system to unknown delays in the input communication channels

Analog Integrated Circuits and Signal Processing
On two-layer brain-inspired hierarchical topologies – a rent's rule approach –

Transactions on High-Performance Embedded Architectures and Compilers IV
Communication and memory architecture design of application-specific high-end multiprocessors

VLSI Design
Scalable communication architectures for massively parallel hardware multi-processors

Journal of Parallel and Distributed Computing
Synthesis of optimized hardware transactors from abstract communication specifications

Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Homogeneous and heterogeneous MPSoC architectures with network-on-chip connectivity for low-power and real-time multimedia signal processing

VLSI Design
Utility accrual object distribution in MPSoC real-time embedded systems

Journal of Computer and System Sciences
Efficient genetic based topological mapping using analytical models for on-chip networks

Journal of Computer and System Sciences
A multi-processor NoC-based architecture for real-time image/video enhancement

Journal of Real-Time Image Processing
Methods for fault tolerance in networks-on-chip

ACM Computing Surveys (CSUR)
Design of massively parallel hardware multi-processors for highly-demanding embedded applications

Microprocessors & Microsystems
Bi-LCQ: A low-weight clustering-based Q-learning approach for NoCs

Microprocessors & Microsystems
Dynamic Power and Thermal Management of NoC-Based Heterogeneous MPSoCs

ACM Transactions on Reconfigurable Technology and Systems (TRETS)

Quantified Score

Hi-index	0.00

Visualization

Abstract

Traditionally, design-space exploration for systems-on-chip (SoCs) has focused on the computational aspects of the problem at hand. However, as the number of components on a single chip and their performance continue to increase, a shift from computation-based to communication-based design becomes mandatory. As a result, the communication architecture plays a major role in the area, performance, and energy consumption of the overall system. This article presents a comprehensive evaluation of three on-chip communication architectures targeting multimedia applications. Specifically, we compare and contrast the network-on-chip (NoC) with point-to-point (P2P) and bus-based communication architectures in terms of area, performance, and energy consumption. As the main contribution, we present complete P2P, bus-, and NoC-based implementations of a real multimedia application (i. e. the MPEG-2 encoder), and provide direct measurements using an FPGA prototype and actual video clips, rather than simulation and synthetic workloads. We also support the experimental findings through a theoretical analysis. Both experimental and analysis results show that the NoC architecture scales very well in terms of area, performance, energy, and design effort, while the P2P and bus-based architectures scale poorly on all accounts except for performance and area, respectively.