MC-Sim: an efficient simulation tool for MPSoC designs

  • Authors:

  • Jason Cong;Karthik Gururaj;Guoling Han;Adam Kaplan;Mishali Naik;Glenn Reinman

  • Affiliations:

  • University of California, Los Angeles Los Angeles, CA;University of California, Los Angeles Los Angeles, CA;University of California, Los Angeles Los Angeles, CA;University of California, Los Angeles Los Angeles, CA;University of California, Los Angeles Los Angeles, CA;University of California, Los Angeles Los Angeles, CA

  • Venue:
  • Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
  • Year:
  • 2008

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Abstract

The ability to integrate diverse components such as processor cores, memories, custom hardware blocks and complex network-on-chip (NoC) communication frameworks onto a single chip has greatly increased the design space available for system-on-chip (SoC) designers. Efficient and accurate performance estimation tools are needed to assist the designer in making design decisions. In this paper, we present MC-Sim, a heterogeneous multi-core simulator framework which is capable of accurately simulating a variety of processor, memory, NoC configurations and application specific coprocessors. We also describe a methodology to automatically generate fast, cycle-true behavioral, C-based simulators for coprocessors using a high-level synthesis tool and integrate them with MC-Sim, thus augmenting it with the capacity to simulate coprocessors. Our C-based simulators provide on an average 45x improvement in simulation speed over that of RTL descriptions. We have used this framework to simulate a number of real-life applications such as the MPEG4 decoder and litho-simulation, and experimented with a number of design choices. Our simulator framework is able to accurately model the performance of these applications (only 7% off the actual implementation) and allows us to explore the design space rapidly and achieve interesting design implementations