DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Hardware emulation for functional verification of K5
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Functional verification methodology for the PowerPC 604 microprocessor
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Functional verification methodology of Chameleon processor
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Virtual chip: making functional models work on real target systems
DAC '98 Proceedings of the 35th annual Design Automation Conference
A transaction-based unified simulation/emulation architecture for functional verification
Proceedings of the 38th annual Design Automation Conference
VHDL, Hardware Description and Design
VHDL, Hardware Description and Design
The VERILOG Hardware Description Language
The VERILOG Hardware Description Language
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
A systematic IP and bus subsystem modeling for platform-based system design
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip
Proceedings of the 43rd annual Design Automation Conference
Multi-processor operating system emulation framework with thermal feedback for systems-on-chip
Proceedings of the 17th ACM Great Lakes symposium on VLSI
HW-SW emulation framework for temperature-aware design in MPSoCs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Accelerating system-on-chip power analysis using hybrid power estimation
Proceedings of the 44th annual Design Automation Conference
A systematic approach to design low-power video codec cores
EURASIP Journal on Embedded Systems
Verification of temporal properties in automotive embedded software
Proceedings of the conference on Design, automation and test in Europe
MC-Sim: an efficient simulation tool for MPSoC designs
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Verifying external interrupts of embedded microprocessor in SoC with on-chip bus
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Efficient Memory Utilization for High-Speed FPGA-Based Hardware Emulators with SDRAMs
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Combined simulation and emulation setup for complex image processing algorithms in VHDL
Proceedings of the 6th FPGAworld Conference
A timed HW/SW coemulation technique for fast yet accurate system verification
SAMOS'09 Proceedings of the 9th international conference on Systems, architectures, modeling and simulation
RTOS-aware refinement for TLM2.0-based HW/SW designs
Proceedings of the Conference on Design, Automation and Test in Europe
FEMU: a firmware-based emulation framework for SoC verification
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A flexible hybrid simulation platform targeting multiple configurable processors SoC
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Emulation-based transient thermal modeling of 2D/3D systems-on-chip with active cooling
Microelectronics Journal
A non-intrusive timing synchronization interface for hardware-assisted HW/SW co-simulation
Proceedings of the 49th Annual Design Automation Conference
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Innovations in Systems and Software Engineering
| Hi-index | 0.00 |
This paper describes a new hardware/software co-verification method for System-On-a-Chip, based on the integration of a C/C++ simulator and an inexpensive FPGA emulator. Communication between the simulator and emulator occurs via a flexible interface based on shared communication registers. This method enables easy debugging, rich portability, and high verification speed, at a low cost. We describe the application of this environment to the verification of three different complex commercial SoCs, supporting concurrent hardware and embedded software development. In these projects, our verification methodology was used to perform complete system verification at 0.2-1.1 MHz, while supporting full graphical interface functions such as "waveform" or "signal dump" viewers, and debugging functions such as "step" or "break".