An approach to instruction set compiled simulator development based on a target processor C compiler back-end design

Authors:
Miodrag Djukic;Nenad Cetic;Radovan Obradovic;Miroslav Popovic
Affiliations:
Faculty of Technical Sciences, University of Novi Sad, Novi Sad, Serbia 21000;Faculty of Technical Sciences, University of Novi Sad, Novi Sad, Serbia 21000;Faculty of Technical Sciences, University of Novi Sad, Novi Sad, Serbia 21000;Faculty of Technical Sciences, University of Novi Sad, Novi Sad, Serbia 21000
Venue:
Innovations in Systems and Software Engineering
Year:
2013

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Abstract

Many instruction set simulation approaches place the retargetability and/or cycle-accuracy as the key features for easier architectural exploration and performance estimation early in the hardware development phase. This paper describes an approach in which importance of speed and controllability is placed above the cycle-accuracy and retargetability, thus providing a better platform for software development. The main idea behind this work is to associate the compiled simulator effort with the development of the C language compiler for the target embedded processor, using the knowledge related to compilers and reusing some common software elements. Through the prototype design of a compiled simulator for the Cirrus Logic Coyote DSP architecture, many implementation aspects are presented showing that this approach has great potential.