Shade: a fast instruction-set simulator for execution profiling
SIGMETRICS '94 Proceedings of the 1994 ACM SIGMETRICS conference on Measurement and modeling of computer systems
Embra: fast and flexible machine simulation
Proceedings of the 1996 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
ISDL: an instruction set description language for retargetability
DAC '97 Proceedings of the 34th annual Design Automation Conference
Generation of software tools from processor descriptions for hardware/software codesign
DAC '97 Proceedings of the 34th annual Design Automation Conference
A retargetable, ultra-fast instruction set simulator
DATE '99 Proceedings of the conference on Design, automation and test in Europe
EXPRESSION: a language for architecture exploration through compiler/simulator retargetability
DATE '99 Proceedings of the conference on Design, automation and test in Europe
A generic tool set for application specific processor architectures
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 14th international symposium on Systems synthesis
Functional abstraction driven design space exploration of heterogeneous programmable architectures
Proceedings of the 14th international symposium on Systems synthesis
A universal technique for fast and flexible instruction-set architecture simulation
Proceedings of the 39th annual Design Automation Conference
An efficient retargetable framework for instruction-set simulation
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Fine-grained application source code profiling for ASIP design
Proceedings of the 42nd annual Design Automation Conference
Memory access optimizations in instruction-set simulators
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Dynamic phase analysis for cycle-close trace generation
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
DynamoSim: a trace-based dynamically compiled instruction set simulator
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Constructing portable compiled instruction-set simulators: an ADL-driven approach
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Proceedings of the 41st annual Design Automation Conference
The ArchC architecture description language and tools
International Journal of Parallel Programming
A retargetable framework for instruction-set architecture simulation
ACM Transactions on Embedded Computing Systems (TECS)
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
B2Sim:: a fast micro-architecture simulator based on basic block characterization
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
HySim: a fast simulation framework for embedded software development
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
A fast and generic hybrid simulation approach using C virtual machine
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
Fast cycle-approximate instruction set simulation
SCOPES '08 Proceedings of the 11th international workshop on Software & compilers for embedded systems
FaCSim: a fast and cycle-accurate architecture simulator for embedded systems
Proceedings of the 2008 ACM SIGPLAN-SIGBED conference on Languages, compilers, and tools for embedded systems
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Processor Description Languages
Processor Description Languages
High Speed CPU Simulation Using LTU Dynamic Binary Translation
HiPEAC '09 Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers
Hybrid-compiled simulation: An efficient technique for instruction-set architecture simulation
ACM Transactions on Embedded Computing Systems (TECS)
Fast and accurate performance simulation of embedded software for MPSoC
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Memory subsystem simulation in software TLM/T models
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Proceedings of the 2nd International Conference on Simulation Tools and Techniques
A Generic Instruction Set Simulator API for Timed and Untimed Simulation and Debug of MP2-SoCs
RSP '09 Proceedings of the 2009 IEEE/IFIP International Symposium on Rapid System Prototyping
An effective synchronization approach for fast and accurate multi-core instruction-set simulation
EMSOFT '09 Proceedings of the seventh ACM international conference on Embedded software
TotalProf: a fast and accurate retargetable source code profiler
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Trace-driven workload simulation method for Multiprocessor System-On-Chips
Proceedings of the 46th Annual Design Automation Conference
A versatile generator of instruction set simulators and disassemblers
SPECTS'09 Proceedings of the 12th international conference on Symposium on Performance Evaluation of Computer & Telecommunication Systems
International Journal of Critical Computer-Based Systems
Generalized just-in-time trace compilation using a parallel task farm in a dynamic binary translator
Proceedings of the 32nd ACM SIGPLAN conference on Programming language design and implementation
A high-parallelism distributed scheduling mechanism for multi-core instruction-set simulation
Proceedings of the 48th Design Automation Conference
The Java Virtual Machine in retargetable, high-performance instruction set simulation
Proceedings of the 9th International Conference on Principles and Practice of Programming in Java
Efficient sampling startup for sampled processor simulation
HiPEAC'05 Proceedings of the First international conference on High Performance Embedded Architectures and Compilers
Exploring design space using transaction level models
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
Statistical Performance Modeling in Functional Instruction Set Simulators
ACM Transactions on Embedded Computing Systems (TECS)
Proceedings of the 13th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, Tools and Theory for Embedded Systems
Journal of Systems Architecture: the EUROMICRO Journal
HyCoS: hybrid compiled simulation of embedded software with target dependent code
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A distributed timing synchronization technique for parallel multi-core instruction-set simulation
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
Innovations in Systems and Software Engineering
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Instruction set simulators are critical tools for the exploration and validation of new programmable architectures. Due to increasing complexity of the architectures and time-to-market pressure, performance is the most important feature of an instruction-set simulator. Interpretive simulators are flexible but slow, whereas compiled simulators deliver speed at the cost of flexibility. This paper presents a novel technique for generation of fast instruction set simulators that combines the benefit of both compiled and interpretive simulation. We achieve fast instruction accurate simulation through two mechanisms. First, we move the time consuming decoding process from run-time to compile time while maintaining the flexibility of the interpretive simulation. Second, we use a novel instruction abstraction technique to generate aggressively optimized decoded instructions that further improves simulation performance. Our instruction set compiled simulation (IS-CS) technique delivers upto 40% performance improvement over the best known published result that has the flexibility of interpretive simulation. We illustrate the applicability of the IS-CS technique using the ARM7 embedded processor.