An ASIP design methodology for embedded systems
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
LISA—machine description language for cycle-accurate models of programmable DSP architectures
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
DSP Cores for Mobile Communications: Where Are We Going?
ICASSP '97 Proceedings of the 1997 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '97) -Volume 1 - Volume 1
A new scalable DSP architecture for system on chip (SoC) domains
ICASSP '99 Proceedings of the Acoustics, Speech, and Signal Processing, 1999. on 1999 IEEE International Conference - Volume 04
Proceedings of the 14th international symposium on Systems synthesis
A universal technique for fast and flexible instruction-set architecture simulation
Proceedings of the 39th annual Design Automation Conference
Design methodology for a modular service-driven network processor architecture
Computer Networks: The International Journal of Computer and Telecommunications Networking - Network processors
Instruction set compiled simulation: a technique for fast and flexible instruction set simulation
Proceedings of the 40th annual Design Automation Conference
An efficient retargetable framework for instruction-set simulation
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A retargetable framework for instruction-set architecture simulation
ACM Transactions on Embedded Computing Systems (TECS)
Hybrid-compiled simulation: An efficient technique for instruction-set architecture simulation
ACM Transactions on Embedded Computing Systems (TECS)
Resource conflict detection in simulation of function unit pipelines
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
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Retargetability allows an easy adoption of a simulator on different processor architectures without a time consuming redesign of all tools. This is evident for an efficient HW/SW codesign.In this paper we describe a tool set for fast and easy simulation of processor architectures based on a retargetable simulator core. This approach helps to reduce the development time for designing and validating System-on-a-chip (SoC) applications based on a processor core. The use of ANSIC avoids an expensive development of a modeling language.Our main focus in this paper is on conceptual decisions we made and on the structure of the tool set.