Random early detection gateways for congestion avoidance
IEEE/ACM Transactions on Networking (TON)
Specification and design of embedded systems
Specification and design of embedded systems
Generating instruction sets and microarchitectures from applications
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
LISA—machine description language for cycle-accurate models of programmable DSP architectures
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A generic tool set for application specific processor architectures
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Designing domain-specific processors
Proceedings of the ninth international symposium on Hardware/software codesign
Computer
Exploring the Design Space of Future CMPs
Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques
Design Tradeoffs for Embedded Network Processors
ARCS '02 Proceedings of the International Conference on Architecture of Computing Systems: Trends in Network and Pervasive Computing
Computer Networks: The International Journal of Computer and Telecommunications Networking - Network processors
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We present a design methodology for a modular network processor architecture that leads to a balanced, servicedefined mix between programmable processor cores, configurable hardware assists, and specialized coprocessors. Whereas the processor cores address the flexibility and extendibility needs of the networking market, the hardware components offload the processors, or even allow them to be bypassed for certain network processor-typical tasks to optimize chip area, performance, and power efficiency. We describe the rationale behind the selected functional partitioning in hardware and software components and discuss the challenges of designing the hardware components, and of organizing and integrating the programmable cores. We quantify our approach with a performance evaluation of the overall system.