DAGON: technology binding and local optimization by DAG matching
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Code generation using tree matching and dynamic programming
ACM Transactions on Programming Languages and Systems (TOPLAS)
Synthesis of instruction sets for pipelined microprocessors
DAC '94 Proceedings of the 31st annual Design Automation Conference
A tool for processor instruction set design
EURO-DAC '94 Proceedings of the conference on European design automation
Instruction selection using binate covering for code size optimization
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
The performance potential of data dependence speculation & collapsing
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
Instruction selection for embedded DSPs with complex instructions
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Low load latency through sum-addressed memory (SAM)
Proceedings of the 25th annual international symposium on Computer architecture
Automatic detection of recurring operation patterns
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
IEEE Transactions on Computers
Design methodology for a modular service-driven network processor architecture
Computer Networks: The International Journal of Computer and Telecommunications Networking - Network processors
Efficient instruction encoding for automatic instruction set design of configurable ASIPs
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Automatic application-specific instruction-set extensions under microarchitectural constraints
Proceedings of the 40th annual Design Automation Conference
Characterizing embedded applications for instruction-set extensible processors
Proceedings of the 41st annual Design Automation Conference
Introduction of local memory elements in instruction set extensions
Proceedings of the 41st annual Design Automation Conference
Automatic application-specific instruction-set extensions under microarchitectural constraints
International Journal of Parallel Programming - Special issue: Workshop on application specific processors (WASP)
A Scalable Application-Specific Processor Synthesis Methodology
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Scalable custom instructions identification for instruction-set extensible processors
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Processor Enhancements for Media Streaming Applications
Journal of VLSI Signal Processing Systems
Satisfying real-time constraints with custom instructions
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Robust header compression (ROHC) in next-generation network processors
IEEE/ACM Transactions on Networking (TON)
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A dynamically constrained genetic algorithm for hardware-software partitioning
Proceedings of the 8th annual conference on Genetic and evolutionary computation
Extracting and improving microarchitecture performance on reconfigurable architectures
International Journal of Parallel Programming - Special issue: The next generation software program
Automatic selection of application-specific instruction-set extensions
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Instruction set synthesis with efficient instruction encoding for configurable processors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Architecture and compiler optimizations for data bandwidth improvement in configurable processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Instruction-set customization for real-time embedded systems
Proceedings of the conference on Design, automation and test in Europe
An efficient framework for dynamic reconfiguration of instruction-set customization
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
An architecture framework for an adaptive extensible processor
The Journal of Supercomputing
Automatic selection of application-specific reconfigurable processor extensions
Proceedings of the conference on Design, automation and test in Europe
The Instruction-Set Extension Problem: A Survey
ARC '08 Proceedings of the 4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
Highly-cited ideas in system codesign and synthesis
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
A scalable synthesis methodology for application-specific processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Constraint-Driven Identification of Application Specific Instructions in the DURASE System
SAMOS '09 Proceedings of the 9th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
Evaluating design trade-offs in customizable processors
Proceedings of the 46th Annual Design Automation Conference
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
Automatic application-specific microarchitecture reconfiguration
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
ISEGEN: an iterative improvement-based ISE generation technique for fast customization of processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The Instruction-Set Extension Problem: A Survey
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
An efficient algorithm for custom instruction enumeration
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
A fast instruction set evaluation method for ASIP designs
EUC'06 Proceedings of the 2006 international conference on Embedded and Ubiquitous Computing
EUC'06 Proceedings of the 2006 international conference on Embedded and Ubiquitous Computing
Accelerating loops for coarse grained reconfigurable architectures using instruction extensions
Proceedings of the 2011 ACM Symposium on Research in Applied Computation
The Journal of Supercomputing
Exact custom instruction enumeration for extensible processors
Integration, the VLSI Journal
Compiling for automatically generated instruction set extensions
Proceedings of the Tenth International Symposium on Code Generation and Optimization
Mixing static and dynamic strategies for high performance and low area reconfigurable systems
International Journal of High Performance Systems Architecture
Accelerating an application domain with specialized functional units
ACM Transactions on Architecture and Code Optimization (TACO)
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We present a semi-automated method for the detection and exploitation of application domain specific instruction set extensions for embedded (VLIW) processors. It consists of three steps: the first step detects frequently occurring operation patterns, in the second step, the patterns are grouped and implemented in a number of Special Function Units (SFUs) and the third step incorporates the custom operations into the code generation process.Experiments show that the SFUs generated and exploited with our methodology can result in architectures that perform up to 30% better than architectures of the same cost without SFUs.