The performance potential of data dependence speculation & collapsing

  • Authors:

  • Yiannakis Sazeides;Stamatis Vassiliadis;James E. Smith

  • Affiliations:

  • Department of Electrical and Computer Engineering, University of Wisconsin-Madison, 1415 Engr. Dr., Madison, WI;Department of Electrical Engineering, Delft University of Technology, Mekelweg 4, 2628 CD Delft, The Netherlands;Department of Electrical and Computer Engineering, University of Wisconsin-Madison, 1415 Engr. Dr., Madison, WI

  • Venue:
  • Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
  • Year:
  • 1996

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Abstract

Two hardware methods for remedying the effects of true data dependences are studied. The first method dependence speculation, is used to eliminate address generation-load dependences. This is enabled by address prediction that permits load instructions to proceed speculatively without waiting for their address operands. The second technique, dependence collapsing, is used to eliminate data dependences by combining a dependence among multiple instructions into one instruction. The potential of these techniques for improving processor performance is demonstrated via trace-driven simulation. When both techniques are used with maximum issue widths of 4, 8, 16, and 32, the overall speedups in comparison to a base instruction level parallel machine are 1.20, 1.35, 1.51, and 1.66, respectively. In general, dependence collapsing contributes the majority of the improvement in performance. Under the dependence collapsing model, 298 to 478 of the total number of instructions in a trace may be collapsed. The distance separating the collapsed instructions is nearly always less than 8. Our experimentation also suggests that further performance improvements can be achieved by incorporating mechanisms that increase the address prediction rate.