A perspective on the 801/Reduced Instruction Set Computer
IBM Systems Journal
The IBM RT PC ROMP processor and memory management unit architecture
IBM Systems Journal
801 storage: architecture and programming
ACM Transactions on Computer Systems (TOCS)
Computation of elementary functions on the IBM RISC System/6000 processor
IBM Journal of Research and Development
ASPLOS I Proceedings of the first international symposium on Architectural support for programming languages and operating systems
The IBM RISC System/6000 processor: hardware overview
IBM Journal of Research and Development
Machine organization of the IBM RISC System/6000 processor
IBM Journal of Research and Development
Design of the IBM RISC System/6000 floating-point execution unit
IBM Journal of Research and Development
Leading-zero anticipator (LZA) in the IBM RISC System/6000 floating-point execution unit
IBM Journal of Research and Development
Evolution of storage facilities in AIX Version 3 for RISC System/6000 processors
IBM Journal of Research and Development
Code generation for streaming: an access/execute mechanism
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
The expandable split window paradigm for exploiting fine-grain parallelsim
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
A comparison of three current superscalar designs
ACM SIGARCH Computer Architecture News
A graphical comparison of RISC processors
ACM SIGARCH Computer Architecture News
On the instruction-level characteristics of scalar code in highly-vectorized scientific applications
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
History of the PowerPC architecture
Communications of the ACM
The PowerPC 603 microprocessor
Communications of the ACM
MOB forms: a class of multilevel block algorithms for dense linear algebra operations
ICS '94 Proceedings of the 8th international conference on Supercomputing
Evolution of the PowerPC Architecture
IEEE Micro
Fine-grain access control for distributed shared memory
ASPLOS VI Proceedings of the sixth international conference on Architectural support for programming languages and operating systems
An Optimal Instruction Scheduler for Superscalar Processor
IEEE Transactions on Parallel and Distributed Systems
Architectural timing verification of CMOS RISC processors
IBM Journal of Research and Development - Special issue: IBM CMOS technology
Fast message assembly using compact address relations
Proceedings of the 1996 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
The performance potential of data dependence speculation & collapsing
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
MIDEE: smoothing branch and instruction cache miss penalties on deep pipelines
MICRO 26 Proceedings of the 26th annual international symposium on Microarchitecture
The Power PC 601 Microprocessor
IEEE Micro
IEEE Transactions on Computers
High-Performance 3-1 Interlock Collapsing ALU's
IEEE Transactions on Computers
Instruction Window Size Trade-Offs and Characterization of Program Parallelism
IEEE Transactions on Computers
A Performance and Cost Analysis of Applying Superscalar Method to Mainframe Computers
IEEE Transactions on Computers
ACM Transactions on Mathematical Software (TOMS)
Proceedings of the 20th annual international conference on Supercomputing
TMA: a trap-based memory architecture
Proceedings of the 20th annual international conference on Supercomputing
Proof of correctness of high-performance 3-1 interlock collapsing ALUs
IBM Journal of Research and Development
A load-instruction unit for pipelined processors
IBM Journal of Research and Development
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