Bulldog: a compiler for VLSI architectures
Bulldog: a compiler for VLSI architectures
A VLIW architecture for a trace Scheduling Compiler
IEEE Transactions on Computers - Special issue on architectural support for programming languages and operating systems
Software pipelining: an effective scheduling technique for VLIW machines
PLDI '88 Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation
Available instruction-level parallelism for superscalar and superpipelined machines
ASPLOS III Proceedings of the third international conference on Architectural support for programming languages and operating systems
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
IBM RISC System/6000 processor architecture
IBM Journal of Research and Development
Compiling techniques for first-order linear recurrences on a vector computer
The Journal of Supercomputing
The SPARC architecture manual: version 8
The SPARC architecture manual: version 8
A high speed superscalar PA-RISC processor
COMPCON '92 Proceedings of the thirty-seventh international conference on COMPCON
Logic Design for a High Performance Mainframe Computer, The HITAC M-880 Processor
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
IBM ES/9000TM System Architecture and Hardware
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Hierarchical Execution to Speed Up Pipeline Interlock in Mainframe Computers
IEEE Transactions on Computers
Performance improvement with circuit-level speculation
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents the results of evaluating the increased performance and cost of mainframe computers with superscalar architectures. Since mainframe users demand object compatibility, we assume the same object as that of nonsuperscalar machines. We compared four differently configured superscalar machines based on Hitachi驴s high-end mainframe computer, the HITAC M-880, varying the multiplicity of operand accessibility and arithmetic capability. In estimating performance, we considered the effect of critical path delay on machine cycle time. For scientific jobs, either dual operand accessibility or dual arithmetic capability, or both, improved performance (MIPS) by 11-28% while increasing CPU hardware cost by 2-21%. For online transaction processing (OLTP), no configuration increased performance more than 4%. To make the superscalar architecture more effective for OLTP, it is important to reduce execution cycles per instruction (CPI), by reducing overhead caused by sequential processes.