Application of instruction analysis/scheduling techniques to resource allocation of superscalar processors

Authors:
Ing-Jer Huang;Ping-Huei Xie
Affiliations:
National Sun Yat-Sen Univ., Taiwan, P.R. China;VIA Technologies, Inc., Taiwan, P.R. China
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2002

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Abstract

This paper presents the development of instruction analysis/scheduling CAD techniques to measure the distribution of functional-unit usage and the microoperation level parallelism (MLP), which together determine the proper functional-unit allocation for superscalar microprocessors, such as the x86 microprocessors. The proposed techniques fit in the early design exploration phase in which the trace or microarchitecture simulator has not been available. The techniques have been applied to analyze several popular Windows95 applications such as Word, Excel, Communicator, etc., for their MLP and distribution of functional-unit usage. The results are used to evaluate the resource allocation of several existing x86 superscalar microprocessors and suggest future extension.