The impact of x86 instruction set architecture on superscalar processing

Authors:
Rafael Rico;Juan-Ignacio Pérez;José Antonio Frutos
Affiliations:
Department of Computer Engineering, Universidad de Alcalá, 28871 Alcala de Henares, Spain;Department of Computer Engineering, Universidad de Alcalá, 28871 Alcala de Henares, Spain;Department of Computer Engineering, Universidad de Alcalá, 28871 Alcala de Henares, Spain
Venue:
Journal of Systems Architecture: the EUROMICRO Journal
Year:
2005

Citing 11
Cited 3

Measuring Parallelism in Computation-Intensive Scientific/Engineering Applications

IEEE Transactions on Computers
An analysis of 8086 instruction set usage in MS DOS programs

ASPLOS III Proceedings of the third international conference on Architectural support for programming languages and operating systems
Available instruction-level parallelism for superscalar and superpipelined machines

ASPLOS III Proceedings of the third international conference on Architectural support for programming languages and operating systems
Limits of instruction-level parallelism

ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
Dynamic dependency analysis of ordinary programs

ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
On the limits of program parallelism and its smoothability

MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Simultaneous multithreading: maximizing on-chip parallelism

ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Application of instruction analysis/scheduling techniques to resource allocation of superscalar processors

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Resolution of data and control-flow dependencies in the PowerPC 601

IEEE Micro
Performance Characterization of the Pentium® Pro Processor

HPCA '97 Proceedings of the 3rd IEEE Symposium on High-Performance Computer Architecture
Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-Order Processors

HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture

Quantifying ILP by means of graph theory

Proceedings of the 2nd international conference on Performance evaluation methodologies and tools
Evaluating x86 condition codes impact on superscalar execution

ISTASC'06 Proceedings of the 6th WSEAS International Conference on Systems Theory & Scientific Computation
Analysis of x86 ISA condition codes influence on superscalar execution

HiPC'07 Proceedings of the 14th international conference on High performance computing

Quantified Score

Hi-index	0.00

Visualization

Abstract

Performance improvement of x86 processors is a relevant matter. From the point of view of superscalar processing, it is necessary to complement the studies on instruction use with analogous ones on data use and, furthermore, analyze the data flow graphs, as its dependencies are responsible for limitations on ILP. In this work, using instruction traces from common applications, quantitative analyses of implicit operands, memory addressing and condition codes have been performed, three sources of significant limitations on the maximum achievable parallelism in the x86 architecture. In order to get a deeper knowledge of these limitations, the data dependence graphs are built from traces. By means of graph matrix representation, potentially exploitable parallelism is quantified and parallelism distributions from the traces are shown. The method has also been applied to measure the impact of the use of condition codes. Results are compared with previous work and some conclusions are presented relating the obtained degree of parallelism with negative characteristics of x86 instruction set architecture.