Evaluating x86 condition codes impact on superscalar execution

Authors:
Virginia Escuder;Raúl Durán;Rafael Rico
Affiliations:
Computer Engineering Department, Universidad de Alcalá, Escuela Politécnica, Alcalá de Henares, Spain;Computer Engineering Department, Universidad de Alcalá, Escuela Politécnica, Alcalá de Henares, Spain;Computer Engineering Department, Universidad de Alcalá, Escuela Politécnica, Alcalá de Henares, Spain
Venue:
ISTASC'06 Proceedings of the 6th WSEAS International Conference on Systems Theory & Scientific Computation
Year:
2006

Citing 4
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Abstract

The design of instruction sets is a fundamental aspect of computer architecture. A critical requirement of instruction set design is to allow for concurrent execution, avoiding those constructs that may produce data dependencies among instructions. Therefore, it is important to count on methods and tools for the evaluation of the behavior of instruction sets and quantify the influence of particular features of its architecture into the overall available parallelism. We propose an analysis method that applies graph theory to gather metrics to evaluate the impact of different characteristics of instruction sets as sources of coupling thus quantifying available parallelism. We present a case study using the x86 instruction set and obtain some measures of the influence of condition flags in code coupling.