Analysis of x86 ISA condition codes influence on superscalar execution

Authors:
Virginia Escuder;Raúl Durán;Rafael Rico
Affiliations:
Department of Computer Engineering, Universidad de Alcalá, Alcalá de Henares, Spain;Department of Computer Engineering, Universidad de Alcalá, Alcalá de Henares, Spain;Department of Computer Engineering, Universidad de Alcalá, Alcalá de Henares, Spain
Venue:
HiPC'07 Proceedings of the 14th international conference on High performance computing
Year:
2007

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Abstract

Instruction sets may have particular characteristics that produce a negative impact into the amount of available parallelism. The x86 instruction set architecture includes some of those characteristics. In particular, it is well know the negative impact of condition codes usage. In a coarse approximation, they can be considered responsible for a greater code coupling. Moreover, several in-depth works show that they introduce additional complexity in the procedures both to perform microcode binary translation and to support for precise exception mechanisms among others. To the extent of our knowledge no quantitative evaluation has been carried out that may determine the impact of condition codes usage on the x86 processors performance. In this work we will present a proposal of such quantification based on Graph Theory.