A VLIW architecture for a trace scheduling compiler
ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
A VLIW architecture for a trace Scheduling Compiler
IEEE Transactions on Computers - Special issue on architectural support for programming languages and operating systems
Exploiting parallel microprocessor microarchitectures with a compiler code generator
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
Optimizing horizontal microprograms for vectorial loops with timed petri nets
ICS '88 Proceedings of the 2nd international conference on Supercomputing
A compilation technique for software pipelining of loops with conditional jumps
ACM SIGMICRO Newsletter
Trace selection for compiling large C application programs to microcode
MICRO 21 Proceedings of the 21st annual workshop on Microprogramming and microarchitecture
The trap as a control flow mechanism
MICRO 21 Proceedings of the 21st annual workshop on Microprogramming and microarchitecture
Proceedings of the 1988 ACM/IEEE conference on Supercomputing
Overlapped loop support in the Cydra 5
ASPLOS III Proceedings of the third international conference on Architectural support for programming languages and operating systems
The fuzzy barrier: a mechanism for high speed synchronization of processors
ASPLOS III Proceedings of the third international conference on Architectural support for programming languages and operating systems
Achieving high instruction cache performance with an optimizing compiler
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
On reordering instruction streams for pipelined computers
MICRO 22 Proceedings of the 22nd annual workshop on Microprogramming and microarchitecture
An Incremental Version of Iterative Data Flow Analysis
IEEE Transactions on Software Engineering
Static synchronization beyond VLIW
Proceedings of the 1989 ACM/IEEE conference on Supercomputing
Region Scheduling: An Approach for Detecting and Redistributing Parallelism
IEEE Transactions on Software Engineering
Profiling an Incremental Data Flow Analysis Algorithm
IEEE Transactions on Software Engineering
VISA: A variable instruction set architecture
ACM SIGARCH Computer Architecture News
Partial evaluation applied to numerical computation
LFP '90 Proceedings of the 1990 ACM conference on LISP and functional programming
Scheduling time-critical instructions on RISC machines
POPL '90 Proceedings of the 17th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Employing register channels for the exploitation of instruction level parallelism
PPOPP '90 Proceedings of the second ACM SIGPLAN symposium on Principles & practice of parallel programming
The Evolution of Instruction Sequencing
Computer - Special issue on instruction sequencing
Mapping concurrent programs to VLIW processors
PPOPP '91 Proceedings of the third ACM SIGPLAN symposium on Principles and practice of parallel programming
Parallelization of loops with exits on pipelined architectures
Proceedings of the 1990 ACM/IEEE conference on Supercomputing
Architectural support for register allocation in the presence of aliasing
Proceedings of the 1990 ACM/IEEE conference on Supercomputing
Architecture and implementation of a VLIW supercomputer
Proceedings of the 1990 ACM/IEEE conference on Supercomputing
The design of a RISC based multiprocessor chip
Proceedings of the 1990 ACM/IEEE conference on Supercomputing
IMPACT: an architectural framework for multiple-instruction-issue processors
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
Automated generation of code using backtracking parsers for attribute grammars
ACM SIGPLAN Notices
Comparing static and dynamic code scheduling for multiple-instruction-issue processors
MICRO 24 Proceedings of the 24th annual international symposium on Microarchitecture
MOVE: a framework for high-performance processor design
Proceedings of the 1991 ACM/IEEE conference on Supercomputing
A semantics-directed partitioning of a processor architecture
Proceedings of the 1991 ACM/IEEE conference on Supercomputing
Processor coupling: integrating compile time and runtime scheduling for parallelism
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Instruction-level parallelism in Prolog: analysis and architectural support
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Inlining semantics for subroutines which are recursive
ACM SIGPLAN Notices
Low level scheduling using the hierarchical task graph
ICS '92 Proceedings of the 6th international conference on Supercomputing
An architectural framework for migration from CISC to higher performance platforms
ICS '92 Proceedings of the 6th international conference on Supercomputing
Predicting conditional branch directions from previous runs of a program
ASPLOS V Proceedings of the fifth international conference on Architectural support for programming languages and operating systems
Code scheduling for VLIW/superscalar processors with limited register files
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Dominator-path scheduling: a global scheduling method
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
StaCS: a Static Control Superscalar architecture
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Compiler code transformations for superscalar-based high performance systems
Proceedings of the 1992 ACM/IEEE conference on Supercomputing
Techniques for integrating parallelizing transformations and compiler-based scheduling methods
Proceedings of the 1992 ACM/IEEE conference on Supercomputing
Precise instruction scheduling without a precise machine model
ACM SIGARCH Computer Architecture News
Balanced scheduling: instruction scheduling when memory latency is uncertain
PLDI '93 Proceedings of the ACM SIGPLAN 1993 conference on Programming language design and implementation
PLDI '93 Proceedings of the ACM SIGPLAN 1993 conference on Programming language design and implementation
Scheduling time-critical instructions on RISC machines
ACM Transactions on Programming Languages and Systems (TOPLAS)
Automatic array alignment in data-parallel programs
POPL '93 Proceedings of the 20th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Sentinel scheduling: a model for compiler-controlled speculative execution
ACM Transactions on Computer Systems (TOCS)
VLIW compilation techniques in a superscalar environment
PLDI '94 Proceedings of the ACM SIGPLAN 1994 conference on Programming language design and implementation
Avoidance and suppression of compensation code in a trace scheduling compiler
ACM Transactions on Programming Languages and Systems (TOPLAS)
Design of heterogeneous ICs for mobile and personal communication systems
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Height reduction of control recurrences for ILP processors
MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
Compiler transformations for high-performance computing
ACM Computing Surveys (CSUR)
An Optimal Instruction Scheduler for Superscalar Processor
IEEE Transactions on Parallel and Distributed Systems
Compiler-Based Multiple Instruction Retry
IEEE Transactions on Computers
Storage assignment to decrease code size
PLDI '95 Proceedings of the ACM SIGPLAN 1995 conference on Programming language design and implementation
Code optimization techniques for embedded DSP microprocessors
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Critical path reduction for scalar programs
Proceedings of the 28th annual international symposium on Microarchitecture
Spill-free parallel scheduling of basic blocks
Proceedings of the 28th annual international symposium on Microarchitecture
ARB: A Hardware Mechanism for Dynamic Reordering of Memory References
IEEE Transactions on Computers
Storage assignment to decrease code size
ACM Transactions on Programming Languages and Systems (TOPLAS)
Symbolic analysis for parallelizing compilers
ACM Transactions on Programming Languages and Systems (TOPLAS)
A register allocation technique using guarded PDG
ICS '96 Proceedings of the 10th international conference on Supercomputing
Strategic directions in computer architecture
ACM Computing Surveys (CSUR) - Special ACM 50th-anniversary issue: strategic directions in computing research
Meld scheduling: relaxing scheduling constraints across region boundaries
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
Data routing: a paradigm for efficient data-path synthesis and code generation
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
A fine-grained MIMD architecture based upon register channels
MICRO 23 Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture
Realistic scheduling: compaction for pipelined architectures
MICRO 23 Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture
High-level microprogramming: an optimizing C compiler for a processing element of a CAD accelerator
MICRO 23 Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture
Post-compaction register assignment in a retargetable compiler
MICRO 23 Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture
An instruction reoderer for pipelined computers
MICRO 23 Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture
Microprogramming heritage of RISC design
MICRO 23 Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture
A compilation technique for software pipelining of loops with conditional jumps
MICRO 20 Proceedings of the 20th annual workshop on Microprogramming
Trace scheduling optimization in a retargetable microcode compiler
MICRO 20 Proceedings of the 20th annual workshop on Microprogramming
Can program profiling support value prediction?
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Simulation/evaluation environment for a VLIW processor architecture
IBM Journal of Research and Development - Special issue: performance analysis and its impact on design
The effect of instruction fetch bandwidth on value prediction
Proceedings of the 25th annual international symposium on Computer architecture
A programmable hardware accelerator for compiled electrical simulation
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
IMPACT: an architectural framework for multiple-instruction-issue processors
25 years of the international symposia on Computer architecture (selected papers)
Using value prediction to increase the power of speculative execution hardware
ACM Transactions on Computer Systems (TOCS)
Effective cluster assignment for modulo scheduling
MICRO 31 Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture
MICRO 31 Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture
MPS: Miss-Path Scheduling for Multiple-Issue Processors
IEEE Transactions on Computers
A partitioning algorithm for system-level synthesis
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Reorganizing global schedules for register allocation
ICS '99 Proceedings of the 13th international conference on Supercomputing
Control flow optimization for supercomputer scalar processing
ICS '89 Proceedings of the 3rd international conference on Supercomputing
A unified semantic approach for the vectorization and parallelization of generalized reductions
ICS '89 Proceedings of the 3rd international conference on Supercomputing
On the control dependence in the program dependence graph
CSC '88 Proceedings of the 1988 ACM sixteenth annual conference on Computer science
ACM SIGPLAN Notices
Modulo scheduling for a fully-distributed clustered VLIW architecture
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Retargetable compilation for low power
Proceedings of the ninth international symposium on Hardware/software codesign
ASPLOS IX Proceedings of the ninth international conference on Architectural support for programming languages and operating systems
Compiling to a VLIW fragment pipeline
Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
Instruction scheduling for clustered VLIW architectures
ISSS '00 Proceedings of the 13th international symposium on System synthesis
CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
Compiler-Assisted Multiple Instruction Word Retry for VLIW Architectures
IEEE Transactions on Parallel and Distributed Systems
Affinity-based cluster assignment for unrolled loops
ICS '02 Proceedings of the 16th international conference on Supercomputing
An interleaved cache clustered VLIW processor
ICS '02 Proceedings of the 16th international conference on Supercomputing
Graph-partitioning based instruction scheduling for clustered processors
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
Modulo scheduling with integrated register spilling for clustered VLIW architectures
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
Embedded software in real-time signal processing systems: design technologies
Readings in hardware/software co-design
Cluster assignment for high-performance embedded VLIW processors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Sunder: a programmable hardware prefetch architecture for numerical loops
Proceedings of the 1994 ACM/IEEE conference on Supercomputing
Computation in the Context of Transport Triggered Architectures
International Journal of Parallel Programming
Meld Scheduling: A Technique for Relaxing Scheduling Constraints
International Journal of Parallel Programming
The Importance of Prepass Code Scheduling for Superscalar and Superpipelined Processors
IEEE Transactions on Computers
A Performance and Cost Analysis of Applying Superscalar Method to Mainframe Computers
IEEE Transactions on Computers
IEEE Transactions on Computers
Compile-Time Techniques for Improving Scalar Access Performance in Parallel Memories
IEEE Transactions on Parallel and Distributed Systems
Making Compaction-Based Parallelization Affordable
IEEE Transactions on Parallel and Distributed Systems
Scheduling DAG's for Asynchronous Multiprocessor Execution
IEEE Transactions on Parallel and Distributed Systems
Generalized Multiway Branch Unit for VLIW Microprocessors
IEEE Transactions on Parallel and Distributed Systems
A Register Allocation Technique Using Register Existence Graph
ICPP '97 Proceedings of the international Conference on Parallel Processing
A Spill Code Placement Framework for Code Scheduling
LCPC '98 Proceedings of the 11th International Workshop on Languages and Compilers for Parallel Computing
Exploiting Pseudo-Schedules to Guide Data Dependence Graph Partitioning
Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques
Increasing and Detecting Memory Address Congruence
Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques
BOKS: A Rule-Based System in Support of the Dutch Building Materials Regulations
Revised Papers from the PRICAI 2000 Workshop Reader, Four Workshops held at PRICAI 2000 on Advances in Artificial Intelligence
High Level Compiling for Low Level Machines
PACT '93 Proceedings of the IFIP WG10.3. Working Conference on Architectures and Compilation Techniques for Fine and Medium Grain Parallelism
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Taming the IXP network processor
PLDI '03 Proceedings of the ACM SIGPLAN 2003 conference on Programming language design and implementation
Memory disambiguation for general-purpose applications
CASCON '95 Proceedings of the 1995 conference of the Centre for Advanced Studies on Collaborative research
The Effectiveness of Loop Unrolling for Modulo Scheduling in Clustered VLIW Architectures
ICPP '00 Proceedings of the Proceedings of the 2000 International Conference on Parallel Processing
A design representation for high level synthesis
EURO-DAC '90 Proceedings of the conference on European design automation
Controlling the data space of tree structured computations
Information and Computation
What can we gain by unfolding loops?
ACM SIGPLAN Notices
FLASH: Foresighted Latency-Aware Scheduling Heuristic for Processors with Customized Datapaths
Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization
Balanced scheduling: instruction scheduling when memory latency is uncertain
ACM SIGPLAN Notices - Best of PLDI 1979-1999
Static Placement, Dynamic Issue (SPDI) Scheduling for EDGE Architectures
Proceedings of the 13th International Conference on Parallel Architectures and Compilation Techniques
Encyclopedia of Computer Science
A cycle-accurate compilation algorithm for custom pipelined datapaths
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A Distributed Control Path Architecture for VLIW Processors
Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Software and hardware techniques to optimize register file utilization in VLIW architectures
International Journal of Parallel Programming
A spatial path scheduling algorithm for EDGE architectures
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Modulo graph embedding: mapping applications onto coarse-grained reconfigurable architectures
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Compiler-assisted leakage energy optimization for clustered VLIW architectures
EMSOFT '06 Proceedings of the 6th ACM & IEEE International conference on Embedded software
Inter-cluster communication in VLIW architectures
ACM Transactions on Architecture and Code Optimization (TACO)
Virtual Cluster Scheduling Through the Scheduling Graph
Proceedings of the International Symposium on Code Generation and Optimization
Heterogeneous Clustered VLIW Microarchitectures
Proceedings of the International Symposium on Code Generation and Optimization
Code and data partitioning for fine-grain parallelism
Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
An Analytical Approach to Scheduling Code for Superscalar and VLIW Architectures
ICPP '94 Proceedings of the 1994 International Conference on Parallel Processing - Volume 01
IEEE Transactions on Computers
Modulo scheduling for highly customized datapaths to increase hardware reusability
Proceedings of the 6th annual IEEE/ACM international symposium on Code generation and optimization
Edge-centric modulo scheduling for coarse-grained reconfigurable architectures
Proceedings of the 17th international conference on Parallel architectures and compilation techniques
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
A Formally Verified Compiler Back-end
Journal of Automated Reasoning
Paper: A boltzmann machine approach to code optimization
Parallel Computing
Runtime Reconfiguration of Multiprocessors Based on Compile-Time Analysis
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
The potential of using dynamic information flow analysis in data value prediction
Proceedings of the 19th international conference on Parallel architectures and compilation techniques
Erasing Core Boundaries for Robust and Configurable Performance
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
An efficient heuristic for instruction scheduling on clustered vliw processors
CASES '11 Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems
HiPC'05 Proceedings of the 12th international conference on High Performance Computing
Trace-Based runtime instruction rescheduling for architecture extension
ICESS'05 Proceedings of the Second international conference on Embedded Software and Systems
Leveraging Strength-Based Dynamic Information Flow Analysis to Enhance Data Value Prediction
ACM Transactions on Architecture and Code Optimization (TACO)
Parallelism improvements of software pipelining by combining spilling with rematerialization
KES'05 Proceedings of the 9th international conference on Knowledge-Based Intelligent Information and Engineering Systems - Volume Part I
Loop transformations in the ahead-of-time optimization of java bytecode
CC'06 Proceedings of the 15th international conference on Compiler Construction
Proceedings of the 13th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, Tools and Theory for Embedded Systems
Compiler supports for VLIW DSP processors with SIMD intrinsics
Concurrency and Computation: Practice & Experience
SCRF: a hybrid register file architecture
PaCT'07 Proceedings of the 9th international conference on Parallel Computing Technologies
ACM Transactions on Embedded Computing Systems (TECS)
Shared-port register file architecture for low-energy VLIW processors
ACM Transactions on Architecture and Code Optimization (TACO)
CAeSaR: unified cluster-assignment scheduling and communication reuse for clustered VLIW processors
Proceedings of the 2013 International Conference on Compilers, Architectures and Synthesis for Embedded Systems
Integrated modulo scheduling and cluster assignment for TI TMS320C64x+ architecture
Proceedings of the 11th Workshop on Optimizations for DSP and Embedded Systems
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