Architecture and implementation of a VLIW supercomputer

Authors:
Robert P. Colwell;W. Eric Hall;Chandra S. Joshi;David B. Papworth;Paul K. Rodman;James E. Tornes
Affiliations:
Multiflow Computer, Inc., 31 Business Park Dr., Branford, CT;Multiflow Computer, Inc., 31 Business Park Dr., Branford, CT;Multiflow Computer, Inc., 31 Business Park Dr., Branford, CT;Multiflow Computer, Inc., 31 Business Park Dr., Branford, CT;Multiflow Computer, Inc., 31 Business Park Dr., Branford, CT;Multiflow Computer, Inc., 31 Business Park Dr., Branford, CT
Venue:
Proceedings of the 1990 ACM/IEEE conference on Supercomputing
Year:
1990

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Abstract

Very-Long-Instruction-Word (VLIW) computers achieve high performance by exploiting the fine-grain parallelism present in sequential or vectorizable code. Multiflow's /200 and /300 VLIW systems yielded near-supercomputer performance by this means despite the relatively slow (65 nS) clocks. With its much faster clock period (15 nS) and architectural improvements, the new /500 system attains approximately 4-9X the performance of its predecessors.This paper describes the /500 architecture and implementation, with special attention paid to the tradeoffs involved in designing very high speed VLIWs.