A Simulation Study of Decoupled Architecture Computers
IEEE Transactions on Computers
Advanced compiler optimizations for supercomputers
Communications of the ACM - Special issue on parallelism
HPSm, a high performance restricted data flow architecture having minimal functionality
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Supercomputer architecture
Pipelining and performance in the VAX 8800 processor
ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
A VLIW architecture for a trace Scheduling Compiler
IEEE Transactions on Computers - Special issue on architectural support for programming languages and operating systems
Reduced instruction set computers
Communications of the ACM - Special section on computer architecture
The Architecture of Symbolic Computers
The Architecture of Symbolic Computers
Design of a Computer—The Control Data 6600
Design of a Computer—The Control Data 6600
Future general purpose supercomputer architectures
Proceedings of the 1990 ACM/IEEE conference on Supercomputing
Architecture and implementation of a VLIW supercomputer
Proceedings of the 1990 ACM/IEEE conference on Supercomputing
ACM SIGARCH Computer Architecture News
Memory latency effects in decoupled architectures with a single data memory module
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
SPAA '93 Proceedings of the fifth annual ACM symposium on Parallel algorithms and architectures
SCISM: a scalable compound instruction set machine
IBM Journal of Research and Development
A Parallel Virtual Machine for Programs Composed of Abstract Data Types
IEEE Transactions on Computers
POWER2 floating-point unit: architecture and implementation
IBM Journal of Research and Development
ARB: A Hardware Mechanism for Dynamic Reordering of Memory References
IEEE Transactions on Computers
Hierarchical Execution to Speed Up Pipeline Interlock in Mainframe Computers
IEEE Transactions on Computers
The 16-fold way: a microparallel taxonomy
MICRO 26 Proceedings of the 26th annual international symposium on Microarchitecture
Boosting beyond static scheduling in a superscalar processor
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Multithreading decoupled architectures for complexity-effective general purpose computing
ACM SIGARCH Computer Architecture News - Special Issue: PACT 2001 workshops
Optimizing a Superscalar Machine to Run Vector Code
IEEE Parallel & Distributed Technology: Systems & Technology
Improved Test Generation for High-Activity Circuits
IEEE Design & Test
IEEE Micro
Memory Latency Effects in Decoupled Architectures
IEEE Transactions on Computers
Code Partitioning in Decoupled Compilers
Euro-Par '00 Proceedings from the 6th International Euro-Par Conference on Parallel Processing
The Decoupled-Style Prefetch Architecture (Research Note)
Euro-Par '00 Proceedings from the 6th International Euro-Par Conference on Parallel Processing
Improved Implementations of the Speculative Memory Access Mechanism specMEM
IWIA '99 Proceedings of the 1999 International Workshop on Innovative Architecture
The Vector-Thread Architecture
Proceedings of the 31st annual international symposium on Computer architecture
Cache Refill/Access Decoupling for Vector Machines
Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture
The Vector-Thread Architecture
IEEE Micro
Design and evaluation of a hierarchical decoupled architecture
The Journal of Supercomputing
| Hi-index | 4.11 |
An overview of and survey solutions to the problem of instruction scheduling for pipelined computers are provided. The author demonstrated that dynamic instruction scheduling can provide performance improvements not possible with static scheduling alone. He describes a high-performance computer, the Astronautics ZS-1, which uses novel methods for implementing dynamic scheduling and which can outperform computers using similar-speed technologies that rely solely on state-of-the-art static scheduling techniques.